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Description: c8051f单片机液晶点阵显示
-128*64,控制器KS0108
试验准备:将拨码开关S1和S2置于ON位置.
运行此程序,LCD将交替显示\"换代创新后的51-高速SOC美国CYGNAL 8051F\"\"新华龙电子-单片机推广应用急先锋!\",\"汉字\".-c8051f SCM LCD dot matrix display -128 * 64, Controller KS0108 test preparations : dial-Switch S1 and S2 placed in the ON position. Run this program. LCD will turn shows that the "innovation and renewal after the 51-high-speed SOC United States CYGNAL 8051F" "Xinhua Long electronic-SCM application vanguard! "," Chinese characters. "
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Size: 12149 |
Author: 周涛 |
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Description: A Built-in Self-Test for Soc
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Size: 527111 |
Author: oho3 |
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Description: c8051f单片机液晶点阵显示
-128*64,控制器KS0108
试验准备:将拨码开关S1和S2置于ON位置.
运行此程序,LCD将交替显示"换代创新后的51-高速SOC美国CYGNAL 8051F""新华龙电子-单片机推广应用急先锋!","汉字".-c8051f SCM LCD dot matrix display-128* 64, Controller KS0108 test preparations : dial-Switch S1 and S2 placed in the ON position. Run this program. LCD will turn shows that the "innovation and renewal after the 51-high-speed SOC United States CYGNAL 8051F" "Xinhua Long electronic-SCM application vanguard! "," Chinese characters. "
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Size: 12288 |
Author: 周涛 |
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Description: samsung推出的s3c2410 soc(可以说是公板)芯片的完整测试代码(官方),外围设备包括ADC,Timer,RTC,IIC,IIS,SPI以及系统的DMA,PLL,Power等.对需要写soc芯片底层驱动的朋友比较有帮助-samsung launched s3c2410 soc (it is a public board) testing of the integrated chip generation (the official), peripheral equipment including ADC, Timer, RTC, IIC, IIS, SPI and the DMA, PLL, Power etc.. need to write high performance chip-driven bottom friends more help
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Size: 1557504 |
Author: cmobile |
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Description: ti-Chipcon CC1010、2510 1G以下Soc应用开发源码实例。包括rf,powermodes,clockmodes底层驱动源码。有了这些实例,包括误码率测试等。对你更好的理解和应用这颗芯片是非常有用的。-ti-Chipcon CC1010, 2510 1G-source application development the following examples Soc. Including rf, powermodes, clockmodes underlying source drive. With these examples, including bit error rate test. You a better understanding and application of this chip is very useful.
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Size: 367616 |
Author: 阿伟 |
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Description: 三星官方S3C2440 SOC PC机端USB Host驱动。包括：secbulk.inf, secbulk.sys, dnw.ini,及其USB Host驱动源程序。-Official Samsung S3C2440 SOC PC-side USB Host driver. Including: secbulk.inf, secbulk.sys, dnw.ini, and USB Host driver source code.
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Size: 926720 |
Author: 琢光 |
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Description: 用于SoC设计的DFT和BIST，讲解了在SOC设计中需要考虑的可测性设计问题
-SoC design for DFT and BIST, explain in the SOC design need to consider design-for-test issues
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Size: 95232 |
Author: godname |
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Description: Samsung S3C2440A SOC RISC Microprocessor test program that demonstrates how to code most peripherals on the chip.
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Size: 2313216 |
Author: idncode |
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Description: 比较经典的SOC设计与测试方法培训教材
第一篇： 概述
第二篇：系统规划
第三篇：测试流程
第四篇：ATPG
第五篇：时序逻辑ATPG和DFT
第六篇：可测试性
第七篇：BIST
第八篇：嵌入式core测试
第九篇：Memory 测试
-Starting with a basic overview of system-on-a-chip (SoC) including definitions of related terms, this text explains SoC design challenges, together with developments in SoC design and and test methodologies.
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Size: 2127872 |
Author: 读卡 |
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Description: generation of wideband high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma–delta modulator chip. Via increasing the order of the one-bit bandpass sigma–delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma–delta modulator chip s production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.- generation of wideband and high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma–delta modulator chip. Via increasing the order of the one-bit bandpass sigma–delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma–delta modulator chip s production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.
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Size: 5120 |
Author: Nupur Naik |
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Description: The SOC test problem is divided into 3 parts.
1)Core Wrapper Design
2)Test Access Mechanism design
3)Test scheduling
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Size: 9461760 |
Author: sornasankar |
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Description: SOC设计验证书籍，有关于芯片设计中的测试部分的研究-SOC design verification of books, the chip design on the part of the test
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Size: 3503104 |
Author: 苏蔚 |
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Description: SOC的可测性设计策略 The SOC design for test strategy-The SOC design for test strategy
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Size: 386048 |
Author: did |
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Description: Jennic 5139/5148 SOC芯片无线测试程序-Jennic 5139/5148 SOC chip developed wireless UART program
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Size: 143360 |
Author: hl |
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Description: Atheros AR71XX AR724X AR913X SoC register definitions for Linux.
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Size: 3072 |
Author: duedaonui |
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Description: Device Tree Include file for Marvell Armada 370 and Armada XP SoC.
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Size: 3072 |
Author: pokanrai |
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Description: 使用Verilog编程搭建的测试平台，并连接了VGA等外设，使用MIPS汇编编写逻辑完成的躲避球小游戏(Use Verilog programming to build the test platform, and connect the VGA and other peripherals, using MIPS assembly to write logic to complete the dodge ball game)
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Size: 12132352 |
Author: 日日夜夜
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Description: # Z-turn-examples
The repository with my simple Z-turn examples, to be used as templates for more serious projects.
Please note, that the Buildroot configuration in my designs sets the root password to "test".
Setting the password is necessary to allow SSH login to the Z-Turn board. Of course you can easily modify that
(either to set a better password or to delete the password at all).
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Size: 2698240 |
Author: forestmeng
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Description: SOC估计是电动汽车电池管理系统的重要功能。研究人员为了提高电动汽车电池SOC估计的准确性做了大量研究工作，采用的主要方法有：放电实验法、Ah计量法、开路电压法、负载电压法、内阻法、线性模型法、神经网络法和卡尔曼滤
波法。讨论了电池SOC定义；介绍了各种SOC估计方法的原理及应用中存在的优缺点；分析了充放电倍率、温度、自放电、老化等因素对SOC的影响；评价了各种SOC估计方法。(SOC estimation was all important function of electric vehicle battery management system. Researchers had done much work to improve SOC estimation accuracy. Discharge test, ampere hour measurement, open circuit voltage, constant current voltage, internal resistance, linear model, neural network and Kalman fiher were taken out. Definition of SOC was discussed, principies of these methods for SOC estimation were intreduced, advantages and disadvantages of these methods during applications were given, factors which influenced SOC estimation, such as charge-discharge rate, temperature, self discharge and aging were analyzed, and these methods were valued.)
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Size: 396288 |
Author: drfang07
|
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Description: 在安时计量方法的基础上, 采用基于折算库仑效率的卡尔曼滤波算法估计蓄电池荷电状态(SOC),并
将此方法应用于 HEV6580混合动力电动汽车镍氢电池管理系统。系统实现的功能包括: 数据监测、数据显示、CAN
通信、SOC估计、热管理和安全报警。经电池试验台模拟工况试验验证, 电池管理系统各子系统达到设计要求且工
作稳定。改进 SOC估计方法解决了传统安时计量法不能估计初始 SOC、难于准确测量库仑效率的问题, 为电池管
理系统稳定工作提供保证(Based on the counting method, using the Calman filter algorithm converting coulomb efficiency estimation based on state of charge (SOC), and
This method is applied to the Ni MH battery management system of HEV6580 hybrid electric vehicle. The functions of the system include: data monitoring, data display, CAN
Communication, SOC estimation, heat management and security alarm. The battery management system has been verified by the simulation test, and the subsystems of the battery management system meet the design requirements and work.
Make it stable. The improved SOC estimation method to solve the SOC, the initial coulombic efficiency are difficult to measure the traditional ampere hour measurement cannot be estimated for the battery tube
Providing guarantee for the stability of the system)
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Size: 442368 |
Author: sulong
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