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Description: 基于fpga和sopc的用VHDL语言编写的EDA含异步清0和同步时钟使能的加法计数器-FPGA and SOPC based on the use of VHDL language with asynchronous EDA-ching 0 and synchronous clock so that the adder counter
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Size: 34816 |
Author: 多幅撒 |
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Description: 用sopc系统在DE2平台上实现一个计数器，该系统包括一个嵌入式微处理器、一个JTAG UART以及定时器-Sopc system implementation with a counter on DE2 platform, the system includes an embedded microprocessor, a JTAG UART and a timer
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Size: 18511872 |
Author: 王锋 |
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