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[ARM-PowerPC-ColdFire-MIPS] mips3

Description: modelsim+dc开发的4级流水线结构的MIPS CPU，完成基本的逻辑运算和跳转。测试程序为希尔排序，结果正确。-modelsim+ dc development of four pipelined structure MIPS CPU, the completion of the basic logic operations and Jump. Test procedure for the Hill to sort the results correctly.
Platform: | Size: 307200 | Author: 杨春 | Hits:

[VHDL-FPGA-Verilog] verilog_risc

Description: RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。 在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前 对这16个数进行排序，从大到小放置在18到33的位置 求出前16个数的平均数，放在34的位置 基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。 因为采用16位指令，有扩充的余地。-RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion.
Platform: | Size: 129024 | Author: lyn | Hits:

[VHDL-FPGA-Verilog] MedFilter_VHDL

Description: 用VHDL实现了Matlab中MedFilt1函数3阶中值滤波。进行排序时没有用软件使用的排序法，而是通过简单的比较实现。-VHDL implementation using the Matlab function MedFilt1 of 3-order median filter. Sort of no use when the software used to sort the Law, but through a simple comparison of implementation.
Platform: | Size: 2048 | Author: mike.chen | Hits:

[VHDL-FPGA-Verilog] DataSort

Description: FPGA内，通过Verilog语言，实现冒泡法数据排序。仅供参考！-FPGA, through the Verilog language, implementation data bubble sort method. For reference purposes only!
Platform: | Size: 5120 | Author: weishiji | Hits:

[Mathimatics-Numerical algorithms] VHDLcode

Description: VHDL code for sort.包括quick sort quick sort -VHDL code for sort. Including the quick sort quick sort, etc.
Platform: | Size: 37888 | Author: 徐飞 | Hits:

[Windows Develop] bubble

Description: this file to sort the input numbers using bubble sort algorithm.-this is file to sort the input numbers using bubble sort algorithm.
Platform: | Size: 1024 | Author: zeeshan | Hits:

[Other Embeded program] lzm_bubble_soft

Description: 基于fpga实现的冒泡排序，初学者研究资料，希望更深一步的进行研究-Fpga-based implementation of bubble sort, beginners research data, hoping to study deeper
Platform: | Size: 1024 | Author: 柳泽明 | Hits:

[Other Embeded program] bubble_verilog

Description: 可综合的基于FPGA实现冒泡排序!资料仅供学习参考，包含tb文件-FPGA-based implementation can be integrated bubble sort! Information for reference purposes only to learn that contains the file tb
Platform: | Size: 1024 | Author: 柳泽明 | Hits:

[VHDL-FPGA-Verilog] PING

Description: 一个甲、乙双方参赛，裁判参与的乒乓球比赛游戏模拟机。用8个发光二极管排成一条直线，以中点为界，两边各代表参赛双方的位置，其中点亮的发光二极管代表“乒乓球”的当前位置，点亮的发光二极管依次由左向右或由右向左移动。当球运动到某方的最后一位时，参赛者应立即按下自己一方的按钮，即表示击球，若击中，则“球”向相反方向运动，若未击中，则对方得1分。设置自动计分电路，双方各用二位数码管来显示计分，每局11分。每人发2球，7局4胜制。自动几分并显示-A A, B both play, the referee in the table tennis game simulator. With 8 LEDs arranged in a straight line, the midpoint for the community, representatives of both sides of the position of participating parties, including light-emitting diodes for " table tennis" in the current location, followed by light-emitting diode, or from left to right moving from right to left. When the ball movement to a party the last one, the participant should immediately press the button on its side, that means the ball, if hit, the " ball" in the opposite direction, if not hit, the other was a points. Automatic scoring circuit, each side with two digital displays scoring 11 points per game. Each made 2 balls, 7 Council 4 match. Automatically sort and display
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] sort

Description: 這個是排序,它可以幫妳把妳像要的數值進行排序-This is the sort that can help you turn on your values to be sorted as
Platform: | Size: 1024 | Author: shiyuanlin | Hits:

[VHDL-FPGA-Verilog] TRABALHO4

Description: It s a sort of problem about sincronous operation using vhdl em DE2. Another homework lesson.
Platform: | Size: 203776 | Author: Marcio | Hits:

[VHDL-FPGA-Verilog] guibing

Description: 该设计采用VHDL语言将五个数的从大到小排序，采用的方法是归并插入排序算法。该算法能在最少比较次数（七次）情况下排列出五个数的大小顺序。-This design using VHDL language will be ordered five digits from big to small, the method is to merge insertion sort algorithm. The proposed algorithm can at least compare (seven) is the size of the discharge list five number sequence.
Platform: | Size: 8882176 | Author: 田慧中 | Hits:

[Other] Sorting

Description: All about sort in C++ code
Platform: | Size: 2952192 | Author: thinhlu123 | Hits:

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