Description: -- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check --- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check Platform: |
Size: 1024 |
Author:leanne |
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Description: 用VHDL写的一个32位并行乘法器的源代码，已经过验证，可以直接使用-Use VHDL to write a 32-bit parallel multiplier source code, has already been verified, you can directly use Platform: |
Size: 1024 |
Author:zh |
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Description: 该源码为8位乘法器的VHDL语言描述，由一个8位右移寄存器，2个4位加法器例化成8位加法器，一个16位数据锁存器构成。采用移位相加的方式，从被乘数的低位开始，与乘数的每个位移位相加求和。最后实现其乘法器功能。-The source code for the 8-bit multiplier in VHDL language to describe, from an 8-bit right shift register, two 4-bit adder example into 8-bit adder, a 16-bit data latch form. Using the sum of the shift, from a low starting multiplicand, the multiplier for each bit shift and summed. Finally, to achieve its multiplier function. Platform: |
Size: 393216 |
Author:feng |
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Search - source code vhdl for 4 bit multiplier