Search - sparten3E

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[Other resource] ug230 DL : 0: xilinx sparten3e 技术文档
Update : 2008-10-13 Size : 6.89mb Publisher : ronghy
[Other resource] Lcddisplay DL : 0: Xilinx sparten3E Lcd显示程序
Update : 2008-10-13 Size : 1.22kb Publisher : ronghy
[Other resource] PS2 DL : 0: Xilinx sparten3E 键盘和开发板的通信和LCD的字符显示
Update : 2008-10-13 Size : 1.59kb Publisher : ronghy
[Other resource] RS232 DL : 0: xilinx Sparten3E 串行通信及lcd字符显示
Update : 2008-10-13 Size : 1.69kb Publisher : ronghy
[Other resource] Sparten3Epaomadeng DL : 0: 通过Xilinx Sparten3E Starter Kit验证程序，开发环境使用的是ISE9.1
Update : 2008-10-13 Size : 1.21mb Publisher : 孙斌
[Other] ug230 DL : 0: xilinx sparten3e 技术文档-xilinx sparten3e technical documentation
Update : 2025-02-17 Size : 6.89mb Publisher : ronghy
[VHDL-FPGA-Verilog] Lcddisplay DL : 0: Xilinx sparten3E Lcd显示程序-Xilinx sparten3E Lcd display program
Update : 2025-02-17 Size : 1kb Publisher : ronghy
[VHDL-FPGA-Verilog] PS2 DL : 0: Xilinx sparten3E 键盘和开发板的通信和LCD的字符显示-Xilinx sparten3E the keyboard and the development board of the Communications and character LCD display
Update : 2025-02-17 Size : 2kb Publisher : ronghy
[VHDL-FPGA-Verilog] RS232 DL : 0: xilinx Sparten3E 串行通信及lcd字符显示-xilinx Sparten3E characters serial communication and lcd display
Update : 2025-02-17 Size : 2kb Publisher : ronghy
[VHDL-FPGA-Verilog] Sparten3Epaomadeng DL : 0: 通过Xilinx Sparten3E Starter Kit验证程序，开发环境使用的是ISE9.1-Xilinx Sparten3E Starter Kit through the verification process, development environment using ISE9.1
Update : 2025-02-17 Size : 1.21mb Publisher : 孙斌
[SCM] Xilinx DL : 0: Xilinx sparten3E 键盘和开发板的通信和LCD的字符显示-Xilinx sparten3E LCD
Update : 2025-02-17 Size : 3kb Publisher : no4
[VHDL-FPGA-Verilog] Spartan3ADSP_MB_Example_10_1 DL : 0: ISE 嵌入式开发实例，主要支持Sparten3E-ISE Embedded Development instance, the main support Sparten3E
Update : 2025-02-17 Size : 227kb Publisher : 钱慧
[VHDL-FPGA-Verilog] digital_clock DL : 0: 用VHDL语言实现常用的数字秒表，并在Sparten3E FPGA上运行通过。-VHDL language commonly used with a digital stopwatch, and Sparten3E FPGA run through.
Update : 2025-02-17 Size : 28.17mb Publisher : 刘勇
[VHDL-FPGA-Verilog] VGA DL : 0: Xilinx sparten3E VGA显示控制程序-Xilinx sparten3E VDisplay and control procedures
Update : 2025-02-17 Size : 1.19mb Publisher : huangfeng
[VHDL-FPGA-Verilog] SCP DL : 0: Xilinx sparten3E 程序串口通信实验程序-Xilinx sparten3E program serial communication experiment procedure
Update : 2025-02-17 Size : 395kb Publisher : huangfeng
[VHDL-FPGA-Verilog] 1 DL : 0: Sparten3E板，通过Xilinx软件实现连续播放音乐的功能。有开始键和复位键-Sparten3E board, playing continuous music
Update : 2025-02-17 Size : 1.28mb Publisher : 李
[VHDL-FPGA-Verilog] digital_voltage DL : 0: VHDL开发的数字电压表，量程5V，精度0.01V，在Sparten3E FPGA运行通过-VHDL development of digital voltmeter, range 5V, precision 0.01V, running through the Sparten3E FPGA
Update : 2025-02-17 Size : 3kb Publisher : 刘勇
[VHDL-FPGA-Verilog] ALU DL : 0: 在Sparten3E上实现4位操作数、3位指令ALU功能，包含7段数码管的译码显示。具有异步清零功能。-Implemented on Sparten3E 4-bit operand, 3 instruction ALU functions, including the 7-segment display decoder. With asynchronous clear function.
Update : 2025-02-17 Size : 234kb Publisher : 潘海智