Search - speech vhdl

[Other resource] pcm(8)

Description: 语音编码的VHDL源码,已经调试通过.压缩文件中包括调试过程代码.-speech coding VHDL source code, debugging has been adopted. Compressed files to include debugging code.
Platform: | Size: 80607 | Author: zhangruqi | Hits:

[Speech/Voice recognition/combine] text2phone

Description: 一个法语的TTS系统，使用perl编写。Text2phone is a French Text To Speech (TTS) written in Perl -a French TTS system, using perl prepared. Text2phone is a French Text To Speech (TTS) writ ten in Perl
Platform: | Size: 14336 | Author: xusihao | Hits:

[VHDL-FPGA-Verilog] pcm(8)

[DSP program] apps

Description: DM6446的codec engine 应用端算法源码，包括video，audio，speech等开发实例。-DM6446-side of the codec engine algorithm source applications, including video, audio, speech, such as the development of examples.
Platform: | Size: 1067008 | Author: bing | Hits:

[Speech/Voice recognition/combine] recognition

Description: 语音识别的源码可用于语音识别。。。。。语音识别的源码可用于语音识别-Speech recognition source code can be used for speech recognition. . . . . Speech recognition source code can be used for speech recognition
Platform: | Size: 4096 | Author: xixi | Hits:

[VHDL-FPGA-Verilog] gencontrol

Description: 高速任意波形产生器控制模块控制NCO,FIFO，并串转换-hign-speed wfgenerator control
Platform: | Size: 1024 | Author: ted yang | Hits:

[Speech/Voice recognition/combine] en_300726v080001p

Description: ETSI EN 300 726 Digital cellular telecommunications systems (Phase 2+) Enhanced Full Rate (EFR) speech transcoding (GSM 06.60)-ETSI EN 300 726 Digital cellular telecommunications systems (Phase 2+) Enhanced Full Rate (EFR) speech transcoding (GSM 06.60)
Platform: | Size: 390144 | Author: swiss | Hits:

[VHDL-FPGA-Verilog] dianyabiao

Description: 基于ISD4004的语音报值交直流电压表的设计：本文介绍了基于语音芯片ISD4004的语音报值交直流电压表的设计。电路由数据采集部分，A/D转换部分，键盘与显示部分，单片机控制部分，语音报值部分和扩展功能部分组成。电路使用了并行与串行总线相结合的方式，使设计与编程灵活简便。创意新颖有趣，富于人性化，避免了频繁观察仪器显示之苦，对减轻工程技术人员的工作量和提高工作效率现实意义。-ISD4004 voice-based value of AC and DC voltage at the design table: In this paper, based on the voice chip ISD4004 voice at the value of AC-DC voltage meter design. Part by the data acquisition circuit, A/D conversion of part of the keyboard and display, single-chip control of the reported value of part of speech and expand the functional parts. The use of a parallel circuit with a combination of serial bus, so as to enable convenient and flexible design and programming. Innovative ideas interesting and full of humanity, to avoid the frequent observation shows that the hardship of equipment, engineering and technical personnel to reduce workload and improve the efficiency of practical significance.
Platform: | Size: 475136 | Author: song | Hits:

[VHDL-FPGA-Verilog] yuyincaiji

Description: 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data storage, faster, 256K* 16Bit selected the SRAM 2. In order to reduce the complexity of single-chip control, the use of the FPGA to control the SRAM The read and write operations, saving a lot of microcontroller I/O resources 3. to future high-speed data storage, the design into the fifo, its width and depth can be set up in the process of free, convenient and flexible.
Platform: | Size: 804864 | Author: song | Hits:

[Speech/Voice recognition/combine] vongrunigen

Description: 语音信号处理，关于语音加密和解密的一个例子-Speech signal processing, voice encryption and decryption on an example of
Platform: | Size: 69632 | Author: 子君 | Hits:

[VHDL-FPGA-Verilog] TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA

Description: Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model’s size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6 correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15 050 logic cells, or about six times less than a current comparable FPGA face detection system.-Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model’s size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6 correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15 050 logic cells, or about six times less than a current comparable FPGA face detection system.
Platform: | Size: 28409856 | Author: ramanaidu | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 对于语音信号的Viterbi算法的简单仿真实现在QuartusII下-Viterbi algorithm for speech signals simple simulation to achieve in the next QuartusII
Platform: | Size: 1024 | Author: 房先生 | Hits:

[Other] MATLAB

Description: 基于 MATLAB 的语音信号分析与处理的课程设计.录制一段自己的语音信号，并对录制的信号进行采样；画出采样后语音信号的时域波形和频谱图；给定滤波器的性能指标，采用窗函数法或双线性变换设计滤波器，并画出滤波器的频率响应；然后用自己设计的滤波器对采集的语音信号进行滤波，画出滤波后信号的时域波形和频谱，并对滤波前后的信号进行对比，分析信号的变化；回放语音信号-MATLAB-based voice signal analysis and processing of the curriculum. Record a voice signal itself, and the recorded signal is sampled draw sampled speech signal time-domain waveform and frequency spectrum filter performance given by using window method or the bilinear transformation to design a filter, and draw the filter frequency response then filter of their own design collection of the speech signal is filtered, the filtered signal to draw the time domain waveform and frequency spectrum, and filter the signal before and after comparison, analysis of signal changes playback voice signal
Platform: | Size: 1201152 | Author: 姚梅 | Hits:

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[Other resource] pcm(8)

[Speech/Voice recognition/combine] text2phone

[VHDL-FPGA-Verilog] pcm(8)

[DSP program] apps

[Speech/Voice recognition/combine] recognition

[VHDL-FPGA-Verilog] gencontrol

[Speech/Voice recognition/combine] en_300726v080001p

[VHDL-FPGA-Verilog] dianyabiao

[VHDL-FPGA-Verilog] yuyincaiji

[Speech/Voice recognition/combine] vongrunigen

[VHDL-FPGA-Verilog] TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA

[VHDL-FPGA-Verilog] viterbi

[Other] MATLAB

[VHDL-FPGA-Verilog] keyboard

[Speech/Voice recognition/combine] FPGADSPBuilder

[VHDL-FPGA-Verilog] etd-0907106-180333

[VHDL-FPGA-Verilog] VHDL100

[VHDL-FPGA-Verilog] 4-_add

[GUI Develop] lpc_recognitionfor-speech-class

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