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Description: communication spi adc for spartan 3e
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Size: 4096 |
Author: hung |
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Description: 本应用指南讲述 Spartan-3E 系列中的串行外设接口 (SPI) 配置模式。SPI 配置模式拓宽了
SpartanTM-3E 设计人员可以使用的配置解决方案。SPI Flash 存储器件引脚少、封装外形小而
且货源广泛。本指南讨论用 SPI Flash 存储器件配置 Spartan-3E FPGA 所需的连接,并且介绍
SPI 模式的配置流程。本指南还提供一种实用工具,用于在原型开发过程中对选定的
STMicroelectronics 和 Atmel SPI 器件进行在系统编程。-Application Guide on the Spartan-3E series of serial peripheral interface (SPI) configuration mode. SPI configuration mode broadened SpartanTM-3E designers can use to configure the solution. SPI Flash memory-pin small package and supply a wide range of small form factor. Discussed in this Guide SPI Flash memory with Spartan-3E FPGA configuration required to connect, and introduced the SPI mode configuration process. This guide also provides a practical tool for the prototype development process in selected STMicroelectronics and Atmel SPI programmable devices in the system.
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Size: 371712 |
Author: xth |
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Description: VHDL code for ADC on Spartan 3E starter kit
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Size: 2048 |
Author: vuu |
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Description: Drive for ADC-DAC POR FPGA SPARTAN 3E STARTER KIT
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Size: 2048 |
Author: FPGA666 |
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Description: The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features:
• Spartan-3E FPGA specific features • Parallel NOR Flash configuration • MultiBoot FPGA configuration from Parallel NOR Flash PROM • SPI serial Flash configuration
• Embedded development • MicroBlazeTM 32-bit embedded RISC processor • PicoBlazeTM 8-bit embedded controller • DDR memory interfaces
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Size: 5851136 |
Author: Akalu Lentiro |
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Description: Spartan 3E - DAC- VHDL.
It is a vhdl code for Xilinx Spartan 3E fpga to run ADC and AMP on the board via SPI interface.
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Size: 157696 |
Author: psycho374 |
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Description: 基于xilinx spartan 3e 开发板的正弦波信号发生,通过fpga查找ROM正弦信号表,将数字信号通过spi接口写入开发板上的12位DA芯片ITC2614。通过DA转换产生正弦波。ROM深度为32768,表示一个正弦周期最多可以有32768个点。可以通过修改相位累积值和ROM表来设定输出正弦波的频率。程序本人编写和上板实测。-Sine wave signal occurred on xilinx spartan 3e development board fpga Find ROM sinusoidal signal table, digital signal through a the spi interface write development board 12 DA chip ITC2614. DA converter to generate a sine wave. The ROM depth 32768, a sinusoidal cycle can have up to 32,768 points. Can be set by modifying the phase accumulation value and the ROM table to the frequency of the sine wave output. Program I write on the board measured.
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Size: 1512448 |
Author: 李华 |
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Description: DAC details has been given for FPGA
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Size: 575488 |
Author: chandra |
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Description: SPI Master Core
HDL: VHDL 93
Compatibility: all FPGAs, CPLDs
parameterization:
- variable data width
- Phase/polarity configurable
- selectable buffer depth
- serial clock devision due to system clock
package usage:
IEEE.STD_LOGIC_1164
IEEE.NUMERIC_STD
work.general_signal_processing_pkg (included)
Testbench for simulation included.
Core Tested on Lattice XP2 CPLD Brevia development kit and FPGAs Xilinx Spartan-3E and Altera Cyclone-4E (industrial application)
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Size: 17408 |
Author: AgentNguyex |
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Description: SPI in VHDL originally designed for Spartan 3e
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Size: 5120 |
Author: Li |
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