Description: spi总线的vhdl代码，试了试可以用。希望能对开发者有所帮助。-spi bus vhdl code Shileshi can use. The hope is to help developers. Platform: |
Size: 343909 |
Author:李鸣 |
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Description: spi总线的vhdl代码，试了试可以用。希望能对开发者有所帮助。-spi bus vhdl code Shileshi can use. The hope is to help developers. Platform: |
Size: 344064 |
Author:李鸣 |
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Description: VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the Platform: |
Size: 65536 |
Author:阿飞 |
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Description: spi总线控制器，包含vhdl和verilog两种代码方式来实现。-spi bus controller, including VHDL and Verilog code in two ways to achieve. Platform: |
Size: 13312 |
Author:wangdong |
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Description: 本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。
本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners. Platform: |
Size: 16035840 |
Author:huangshengqun |
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Description: spi总线的vhdl代码，试了了试能用。希望能对开发者有所帮助。
-spi bus vhdl code, try the test can be used. The hope is to help developers. Platform: |
Size: 345088 |
Author:mx |
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