Search - spi core vhdl

[Embeded-SCM Develop] adda_spi

Description: 这个源码是用altera公司的开发工具NIOS II IDE开发的基于软核处理器的AD、DA控制程序，通过spi 核控制AD、DA的时序，实现正弦波发送和接收-this source is altera company development tools NIOS II IDE- based soft-core Office JIMMY of AD and DA control procedures, spi nuclear control AD and DA timetables to achieve sine sending and receiving
Platform: | Size: 66560 | Author: zeng xuan | Hits:

[VHDL-FPGA-Verilog] spi_op_core

Description: 串行数据SPI master的开源控制器，verilog，内附说明-SPI master serial data open-source controller, verilog, containing a description
Platform: | Size: 81920 | Author: 王天 | Hits:

[VHDL-FPGA-Verilog] EP2C5Q208

Description: 以cyclone系列的EP2C5Q208为核心的实验板程序.包括流水灯,I2C存储器.SPI存储器,数码管,串口,LCD等-Cyclone in series as the core EP2C5Q208 experimental procedure. Including water lights, I2C memory. SPI memory, digital control, serial port, LCD, etc.
Platform: | Size: 2980864 | Author: sarah | Hits:

[VHDL-FPGA-Verilog] spi_master

Description: 基于CPLD/FPGA的SPI控制的IP核的实现spi_master-Based on CPLD/FPGA to control the SPI realize the IP core spi_master
Platform: | Size: 1024 | Author: linsky | Hits:

[Embeded-SCM Develop] spiinterfaceverilog

Description: SPI Master Core Specification，This document provides specifications for the SPI (Serial Peripheral Interface) Master core-SPI Master Core Specification, This document provides specifications for the SPI (Serial Peripheral Interface) Master core
Platform: | Size: 82944 | Author: 贾远鸿 | Hits:

[VHDL-FPGA-Verilog] SPI_verilog_vhdl

Description: SPI串口的内核实现（分别使用verilog和vhdl语言描述的）-The core of the realization of SPI serial port (using Verilog and VHDL language description of the)
Platform: | Size: 13312 | Author: 徐剑 | Hits:

[Embeded-SCM Develop] spi_op_core

Description: SPI协议的Verilog编程，包括时钟的产生模块，控制模块等-Verilog programming SPI protocol, including the selection of the clock module, control module, etc.
Platform: | Size: 82944 | Author: zhangyi | Hits:

[VHDL-FPGA-Verilog] 43680540SPI_Core

Description: Verilog for SPI Core source code
Platform: | Size: 14336 | Author: J.M Yang | Hits:

[VHDL-FPGA-Verilog] spi_op_core

Description: spi controller SPI IP core
Platform: | Size: 81920 | Author: denny | Hits:

[VHDL-FPGA-Verilog] spimaster

Description: SPI IP core supporting SD/MMC
Platform: | Size: 2269184 | Author: zhanglh | Hits:

[VHDL-FPGA-Verilog] simple_spi

Description: complete spi core written in vhdl. its easy to use and can be configured to operate at various clock frequencies. tested on an ADC to verify the operation
Platform: | Size: 584704 | Author: Shahzad | Hits:

[VHDL-FPGA-Verilog] l1ghVhVI

Description: The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
Platform: | Size: 226304 | Author: aaa | Hits:

[VHDL-FPGA-Verilog] CoreSPI_21_eval

Description: SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages Verilog and VHDL source code
Platform: | Size: 628736 | Author: 任林枫 | Hits:

[VHDL-FPGA-Verilog] SPI-Master-Core-DAC-ADC-spartan

Description: SPI Master Core for spartan (ADC, DAC) vhdl code
Platform: | Size: 1961984 | Author: onur | Hits:

[assembly language] SPI-Core_nguyen

Description: SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE.STD_LOGIC_1164 IEEE.NUMERIC_STD work.general_signal_processing_pkg (included) Testbench for simulation included. Core Tested on Lattice XP2 CPLD Brevia development kit and FPGAs Xilinx Spartan-3E and Altera Cyclone-4E (industrial application)
Platform: | Size: 17408 | Author: AgentNguyex | Hits:

[VHDL-FPGA-Verilog] spi_master_module

Description: Simple VHDL SPI-module core source code (only spi-master)
Platform: | Size: 1024 | Author: Alex | Hits:

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[Embeded-SCM Develop] adda_spi

[VHDL-FPGA-Verilog] spi_op_core

[VHDL-FPGA-Verilog] EP2C5Q208

[VHDL-FPGA-Verilog] spi_master

[Embeded-SCM Develop] spiinterfaceverilog

[VHDL-FPGA-Verilog] SPI_verilog_vhdl

[Embeded-SCM Develop] spi_op_core

[VHDL-FPGA-Verilog] 43680540SPI_Core

[VHDL-FPGA-Verilog] spi_op_core

[VHDL-FPGA-Verilog] spimaster

[VHDL-FPGA-Verilog] simple_spi

[VHDL-FPGA-Verilog] l1ghVhVI

[VHDL-FPGA-Verilog] CoreSPI_21_eval

[VHDL-FPGA-Verilog] SPI-Master-Core-DAC-ADC-spartan

[assembly language] SPI-Core_nguyen

[VHDL-FPGA-Verilog] spi_master_module

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