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[VHDL-FPGA-Verilog] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2048 | Author: wyl | Hits:

[VHDL-FPGA-Verilog] I2C_HDL

Description: I2C bus HDL source and testbench
Platform: | Size: 701440 | Author: liuKe | Hits:

[VHDL-FPGA-Verilog] spi_master

Description: 基于CPLD/FPGA的SPI控制的IP核的实现spi_master-Based on CPLD/FPGA to control the SPI realize the IP core spi_master
Platform: | Size: 1024 | Author: linsky | Hits:

[Com Port] pwm16bits

Description: SPI总线Master的verilog代码-SPI Bus Master of Verilog code
Platform: | Size: 1024 | Author: xudong | Hits:

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