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[VHDL-FPGA-Verilog] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2048 | Author: wyl | Hits:

[VHDL-FPGA-Verilog] SimpleSpi

Description: master spi的源代码（verilog），包括文档，测试程序-master spi the source code (verilog), including documentation, testing procedures
Platform: | Size: 180224 | Author: wood | Hits:

[VHDL-FPGA-Verilog] spi_op_core

Description: 串行数据SPI master的开源控制器，verilog，内附说明-SPI master serial data open-source controller, verilog, containing a description
Platform: | Size: 81920 | Author: 王天 | Hits:

[SCM] mcu-cpld-spi

Description: mcu与cpld之间spi接口程序，mcu为master，cpld用verilog写成slave模块-mcu with spi interface program between the CPLD, mcu for the master, cpld written using Verilog slave module
Platform: | Size: 110592 | Author: 叶灿 | Hits:

[Com Port] pwm16bits

Description: SPI总线Master的verilog代码-SPI Bus Master of Verilog code
Platform: | Size: 1024 | Author: xudong | Hits:

[Com Port] spi

Description: SPI master的verilog代码-Verilog code for SPI master
Platform: | Size: 2048 | Author: xudong | Hits:

[Other] spi.tar

Description: This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
Platform: | Size: 1024 | Author: johnl | Hits:

[MPI] spi_verilog

Description: 实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.
Platform: | Size: 45056 | Author: davi_insist | Hits:

[VHDL-FPGA-Verilog] SpiMaster

Description: This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate
Platform: | Size: 9216 | Author: RutaliMulye | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
Platform: | Size: 290816 | Author: 阿虎 | Hits:

[VHDL-FPGA-Verilog] modelsim

Description: verilog SPI master 的完整实验报告 仅供参考 切勿抄袭-verilog SPI master
Platform: | Size: 45056 | Author: ying ma | Hits:

[VHDL-FPGA-Verilog] SPI_Master

Description: verilog HDL 语言描述的8位并行转SPI程序-verilog HDL language description of the 8-bit parallel transfer SPI program
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] spi-master

Description: code for Master side
Platform: | Size: 121856 | Author: suni | Hits:

[VHDL-FPGA-Verilog] SPI-Master-master

Description: Use code for Maser SPI
Platform: | Size: 12288 | Author: suni | Hits:

[VHDL-FPGA-Verilog] SPI_master

Description: spi-master模块的verilog(simple program for SPI-Master)
Platform: | Size: 1024 | Author: jxls378816 | Hits:

[VHDL-FPGA-Verilog] Nitro-Parts-lib-SPI-master

Description: Nitro-Parts-lib-SPI Verilog SPI master and slave
Platform: | Size: 5120 | Author: d.pershin | Hits:

[Com Port] Master SPI的Verilog源代码(包括文档 测试程序)

Description: SPI接口的从机实现（利用verilog HDL语言）(Slave implementation of SPI interface (using Verilog HDL language))
Platform: | Size: 185344 | Author: 够歇斯底里吗 | Hits:

[VHDL-FPGA-Verilog] spi master slave

Description: SPI master slave (fpga/verilog)
Platform: | Size: 67584 | Author: taso999 | Hits:

[Other] spi_verilog_master_slave_latest.tar

Description: spi 的verilog rtl 代码, 包括整体仿真环境，测试码等(spi master or slave verilog rtl code)
Platform: | Size: 3072 | Author: jekky888888 | Hits:

[Other] spi_masterSPI Master 的Verilog源代码

Description: 实现SPI主站通信功能,感兴趣的可以下载。(spi master use verilog.)
Platform: | Size: 133120 | Author: wenyiwenni | Hits:
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