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[Other resource] SimpleSpi

Description: master spi的源代码（verilog），包括文档，测试程序-master spi the source code (verilog), including documentation, testing procedures
Platform: | Size: 180597 | Author: wood | Hits:

[VHDL-FPGA-Verilog] SimpleSpi

Description: master spi的源代码（verilog），包括文档，测试程序-master spi the source code (verilog), including documentation, testing procedures
Platform: | Size: 180224 | Author: wood | Hits:

[Com Port] pwm16bits

Description: SPI总线Master的verilog代码-SPI Bus Master of Verilog code
Platform: | Size: 1024 | Author: xudong | Hits:

[Com Port] spi

Description: SPI master的verilog代码-Verilog code for SPI master
Platform: | Size: 2048 | Author: xudong | Hits:

[Other] spi.tar

Description: This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
Platform: | Size: 1024 | Author: johnl | Hits:

[VHDL-FPGA-Verilog] FPGASPI

Description: 用FPGA实现主SPI程序,包含开发工程、测试文件和源文件代码-fpga design the SPI code
Platform: | Size: 301056 | Author: Lee | Hits:

[MPI] spi_verilog

Description: 实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.
Platform: | Size: 45056 | Author: davi_insist | Hits:

[VHDL-FPGA-Verilog] SpiMaster

Description: This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate
Platform: | Size: 9216 | Author: RutaliMulye | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
Platform: | Size: 290816 | Author: 阿虎 | Hits:

[Algorithm] loschoros

Description: SPI master verilog code
Platform: | Size: 454656 | Author: ignacio | Hits:

[VHDL-FPGA-Verilog] SPI-verilog

Description: spi master code for fpga quartus altera
Platform: | Size: 355328 | Author: djawad | Hits:

[VHDL-FPGA-Verilog] FPGA_SPI

Description: 本源码是用verilog语言编写的FPGA的SPI主机代码，可以用做SPI开发参考。-The source code is written in verilog FPGA SPI master code, can be used to develop a reference SPI.
Platform: | Size: 3072 | Author: 黄华 | Hits:

[VHDL-FPGA-Verilog] SPI-Master

Description: 有关Verilog的SPI通信的代码,可以应用于FPGA的通信-this is verilog code about SPI
Platform: | Size: 3072 | Author: baiyurong | Hits:

[Other] tiny_spi_latest.tar

Description: SPI master 的verilog源码，具有很好的学习价值。-Master SPI Verilog source code, has a good learning value.
Platform: | Size: 10240 | Author: 李伟 | Hits:

[Other Embeded program] spi

Description: It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.-It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.
Platform: | Size: 2048 | Author: eren | Hits:

[VHDL-FPGA-Verilog] spimaster.tar

Description: SPI Interface Master Control RTL Verilog Code
Platform: | Size: 2554880 | Author: richman | Hits:

[VHDL-FPGA-Verilog] SPI_TEST

Description: verilog SPI 读写时序，测试验证OK.-SPI Verilog Code, Master and Slaver.
Platform: | Size: 16368640 | Author: zhufull | Hits:

[VHDL-FPGA-Verilog] spi-master

Description: code for Master side
Platform: | Size: 121856 | Author: suni | Hits:

[VHDL-FPGA-Verilog] SPI-Master-master

Description: Use code for Maser SPI
Platform: | Size: 12288 | Author: suni | Hits:

[Other] spi_verilog_master_slave_latest.tar

Description: spi 的verilog rtl 代码, 包括整体仿真环境，测试码等(spi master or slave verilog rtl code)
Platform: | Size: 3072 | Author: jekky888888 | Hits:
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