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[Other resourcegeneric_avalon_sram

Description: 一个比较有参考价值的sram IP核,对SOPC感兴趣的人士有一定的指导意义!该程序是采用avalon总线,可以直接内嵌进SOPC Builder。
Platform: | Size: 5534 | Author: 林盈 | Hits:

[Other resourcealtera_avalon_cy7c1380_ssram

Description: 关于altera的SRAM的读写控制IP代码,有兴趣的朋友可以下去
Platform: | Size: 7200 | Author: liufanyu | Hits:

[Other resourceSRAMCotroller

Description: 一个SRAM控制器的IP核,很不错,有兴趣的朋友可以下去
Platform: | Size: 322449 | Author: liufanyu | Hits:

[Other resourceSRAM_16Bit_512K

Description: Verilog 编写的IP核,512K的16位SRAM
Platform: | Size: 11531 | Author: zhyy | Hits:

[VHDL-FPGA-Veriloggeneric_avalon_sram

Description: 一个比较有参考价值的sram IP核,对SOPC感兴趣的人士有一定的指导意义!该程序是采用avalon总线,可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.
Platform: | Size: 5120 | Author: 林盈 | Hits:

[Other Embeded programSRAM_16Bit_512K

Description: DE2板子附带的SRAM IPCORE 有兴趣的朋友可以下载-DE2 board attached SRAM IPCORE friends who are interested can download
Platform: | Size: 11264 | Author: huang | Hits:

[Other Embeded programaltera_avalon_cy7c1380_ssram

Description: 关于altera的SRAM的读写控制IP代码,有兴趣的朋友可以下去-On the SRAM
Platform: | Size: 7168 | Author: liufanyu | Hits:

[Other Embeded programSRAMCotroller

Description: 一个SRAM控制器的IP核,很不错,有兴趣的朋友可以下去-An SRAM controller IP core, very good friends who are interested can go on
Platform: | Size: 322560 | Author: liufanyu | Hits:

[VHDL-FPGA-VerilogSRAM_16Bit_512K

Description: Verilog 编写的IP核,512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM
Platform: | Size: 11264 | Author: zhyy | Hits:

[VHDL-FPGA-VerilogDE2_NIOS_LITE_SRAM

Description: DE2-SRAM-IP-CORE 需要开发ip core的朋友可以参考哦 ~-DE2-SRAM-IP-CORE need to develop friends can ip core reference Oh ~
Platform: | Size: 1573888 | Author: 张曦 | Hits:

[VHDL-FPGA-Verilogaltera_up_avalon_sram

Description: 基于Avalon的SDRAM控制器IP核-Avalon SRAM Controller
Platform: | Size: 320512 | Author: 涂登乾 | Hits:

[VHDL-FPGA-VerilogProtecting_FPGA

Description: How to protect your FPGA design (IP) on SRAM based FPGA s against copying.
Platform: | Size: 1542144 | Author: TR | Hits:

[VHDL-FPGA-VerilogSRAM_Controller

Description: Altera University Program的Avalon总线IP核,SRAM控制代码,可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
Platform: | Size: 324608 | Author: vicky | Hits:

[Other Embeded programSRAM_Controller

Description: altera 大学计划 程序包的sram controller ip-altera University Program package sram controller ip
Platform: | Size: 218112 | Author: suwen | Hits:

[Software Engineeringram_top

Description: arm ahb slave bus sram ip in verilog
Platform: | Size: 2048 | Author: msd | Hits:

[VHDL-FPGA-VerilogALTERA_SRAM_IP

Description: ALTERA公司的SRAM IP核,加快设计流程-ALTERA company SRAM IP cores, speeding up the design process
Platform: | Size: 146432 | Author: sqf | Hits:

[VHDL-FPGA-VerilogSRAM_16Bit_512K_0

Description: SRAM的ip核,niosii,avalon总线的-SRAM' s ip nuclear, niosii, avalon bus
Platform: | Size: 1024 | Author: 吴敬飞 | Hits:

[VHDL-FPGA-Verilogmb_support_sram

Description: 配置MB软核使其支持,SRAM并在此基础上做UART测试,文章(我写的呵呵)详细的讲了如何从最对SRAM时序进行配置,如何设置相应参数,如何生成硬件平台,实在是入门必备。-configure the MB ip core to support SRAM .and ,do a test with dsp uart
Platform: | Size: 358400 | Author: hound | Hits:

[VHDL-FPGA-VerilogSRAM

Description: 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
Platform: | Size: 9216 | Author: 于洋 | Hits:

[VHDL-FPGA-VerilogHEX2MIF

Description: QUARTUS II SRAM/ROM初始化需要的HEX文件与Keil产生的HEX格式不同;该Modelsim程序,将Keil产生的Hex转换成,Quartus可以是识别的MIF格式;(The QUARTUS II SRAM/ROM initialization needs HEX files which are different from those generated by Keil. The Modelsim program converts Hex generated by Keil to Quartus, which can be recognized as the MIF format.)
Platform: | Size: 1024 | Author: MCUMaster | Hits:
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