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Description: 一个比较有参考价值的sram IP核,对SOPC感兴趣的人士有一定的指导意义!该程序是采用avalon总线,可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.
Platform: |
Size: 5120 |
Author: 林盈 |
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Description: DE2板子附带的SRAM IPCORE 有兴趣的朋友可以下载-DE2 board attached SRAM IPCORE friends who are interested can download
Platform: |
Size: 11264 |
Author: huang |
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Description: 一个SRAM控制器的IP核,很不错,有兴趣的朋友可以下去-An SRAM controller IP core, very good friends who are interested can go on
Platform: |
Size: 322560 |
Author: liufanyu |
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Description: Verilog 编写的IP核,512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM
Platform: |
Size: 11264 |
Author: zhyy |
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Description: DE2-SRAM-IP-CORE
需要开发ip core的朋友可以参考哦
~-DE2-SRAM-IP-CORE need to develop friends can ip core reference Oh ~
Platform: |
Size: 1573888 |
Author: 张曦 |
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Description: Altera University Program的Avalon总线IP核,SRAM控制代码,可以解压后直接挂载在Avalon总线上
-Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
Platform: |
Size: 324608 |
Author: vicky |
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Description: 配置MB软核使其支持,SRAM并在此基础上做UART测试,文章(我写的呵呵)详细的讲了如何从最对SRAM时序进行配置,如何设置相应参数,如何生成硬件平台,实在是入门必备。-configure the MB ip core to support SRAM .and ,do a test with dsp uart
Platform: |
Size: 358400 |
Author: hound |
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Description: 使用Verilog语言编写的SRAM读写程序,不用添加IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-SRAM using Verilog language literacy program, do not add the IP core in Xilinx Spartan-6 run through, is a very good program Verlog
Platform: |
Size: 9216 |
Author: 于洋 |
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