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[Other resource] leon3-altera-ep2s60-ddr DL : 0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Update : 2008-10-13 Size : 112.09kb Publisher : king.xia
[SCM] chip45boot_060814 DL : 0: AVR的引导程序。 chip45boot s-record bootloader.-AVR guidance procedures. Chip45boot s-record Bootloader.
Update : 2025-02-17 Size : 32kb Publisher :
[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr DL : 0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Update : 2025-02-17 Size : 112kb Publisher :
[ARM-PowerPC-ColdFire-MIPS] srecord-v1 DL : 0: HEX file converter for motorola, intel format and merge file function
Update : 2025-02-17 Size : 1.75mb Publisher : john lee
[Other] srecord-1.64-win32 DL : 1: srecord hex to bin / bin to hex
Update : 2025-02-17 Size : 1.88mb Publisher : k1v1116