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[Other resource] divider DL : 0: 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。
Update : 2008-10-13 Size : 2.27kb Publisher : 朱秋玲
[Other resource] divider DL : 0: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）
Update : 2008-10-13 Size : 2.86kb Publisher : 刘蒲霞
[MPI] arban DL : 0: 这是一个用verilog实现的除法器代码。-This is a realization of the use verilog divider code.
Update : 2025-02-17 Size : 1kb Publisher : arban
[VHDL-FPGA-Verilog] divider DL : 1: 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。-This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-point divider number (divisor, dividend and the remainder by the 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 decimal places, including the source code and test files, you can direct simulation.
Update : 2025-02-17 Size : 2kb Publisher : 朱秋玲
[VHDL-FPGA-Verilog] divider DL : 0: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)
Update : 2025-02-17 Size : 3kb Publisher : 刘蒲霞
[Documents] srt-2 DL : 0: 台湾大学电子所讲义，介绍srt-2算法以及更高基的算法-National Taiwan University of Electronics Materials, Introduction srt-2 algorithm, as well as a higher-based algorithms
Update : 2025-02-17 Size : 768kb Publisher : 刘蒲霞
[VHDL-FPGA-Verilog] SRT DL : 0: verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient output [8:0]Remainder -verilog coderadix-2 SRT dividerinput [7:0] Dividend input [3:0] Divisor output [4:0] Quotient output [8:0] Remainder
Update : 2025-02-17 Size : 2kb Publisher : 沙嗲
[ARM-PowerPC-ColdFire-MIPS] 5956447divider DL : 0: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the 32-bit integer and 16-bit fractional composition, I composed a few from the 32-bit decimal)
Update : 2025-02-17 Size : 3kb Publisher : wfwef