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Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)
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Size: 3072 |
Author: 刘蒲霞 |
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Description: 台湾大学电子所讲义，介绍srt-2算法以及更高基的算法-National Taiwan University of Electronics Materials, Introduction srt-2 algorithm, as well as a higher-based algorithms
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Size: 786432 |
Author: 刘蒲霞 |
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Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the 32-bit integer and 16-bit fractional composition, I composed a few from the 32-bit decimal)
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Size: 3072 |
Author: wfwef |
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Description: 模拟进程调度，给出按照算法先来先服务FCFS、轮转RR（q=1）、最短进程优先SPN、最短剩余时间SRT、最高响应比优先HRRN进行调度各进程的完成时间、周转时间、响应比的值。-The simulation process scheduling, given in accordance with the algorithm first-come, first-served FCFS, rotary RR (q = 1), the shortest process priority the SPN, the shortest time remaining SRT, the highest response than the completion time of the scheduling process priority HRRN, turnaround time, response ratio value.
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Size: 159744 |
Author: 高莹 |
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Description: 两种快速排序算法的实现-Two implementation of quicksort algorithm
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Size: 1024 |
Author: 宋黑 |
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Description: 进程调度
模拟进程调度，给出按照算法先来先服务FCFS、轮转RR（q=1）、最短进程优先SPN、最短剩余时间SRT、最高响应比优先HRRN进行调度各进程的完成时间、周转时间、响应比的值-Process scheduling simulation process scheduling algorithm is given in accordance with the first-come, first-served FCFS, rotate RR (q = 1), the shortest process priority SPN, the shortest time remaining SRT, the maximum response time than the scheduling priority HRRN be completed for each process, turnaround time, response ratio
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Size: 2048 |
Author: nego |
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