Description: 文章详细介绍了VHDL中状态机的设计,结合图形解释,对于初学者很有帮助-article describes in detail the state machine in VHDL design, integrating graphics explain helpful for beginners Platform: |
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Author:吴林煌 |
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Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test Platform: |
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Author: |
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Description: 此模块用 ＶＨＤＬ 硬件描述语言来实现，对键盘设计的实际操作检验表明，此模块响应迅速、识别准确，较好地实现了键盘扫描和去抖动功能， 达到了预期的设计目的。同时，将状态机、扫描线、计数器等相关参数稍作改动，就可以扩展到实现不同键盘矩阵的设计-VHDL hardware description language to achieve the keyboard design of the actual operation of testing show that This module in response to the rapid, accurate identification, a better way to realize the keyboard scan and jitter to function, to achieve the desired purpose. Meanwhile, the state machine, scanning lines, counter and other related parameters minor modifications, it can be extended to the realization of the different design of the keyboard matrix Platform: |
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Author:章菁 |
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Description: Verilog and VHDL状态机设计，英文pdf格式
State machine design techniques for Verilog and VHDL
Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in
engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding
presented. Different methodologies will be compared using real-world examples.-Verilog and VHDL state machine design, English pdf format State machine design techniques for Ve rilog and VHDL Abstract : Designing a synchronous finite state Another w ay of organizing a state machine (FSM) is a commo n task for a digital logic only one logic block as shown in engineer. This paper will discuss a var iety of issues regarding FSM design using Synop sys Design Compiler. Verilog and VHDL coding st yles will be 2.0 Basic HDL coding presented. Dif ferent methodologies will be compared using're al-world examples. Platform: |
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Author:mingming |
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Description: MEALY状态机的输出是现态和输入的函数.在SRAM控制器状态机中,写有效WE不仅和WRITE状态有关,还和总线命令WRITE_MASK有关.这样,输出WE信号按设计要求表示为现态WRITE和现态输入WRITE_MASK的函数.本程序基于VHDL,开发环境为MAXPLUS2-Mealy state machine output is now a function of state and input. In the SRAM controller state machine, the writing is not only effective WE and WRITE state, but also and bus-related WRITE_MASK command. In this way, WE output signal according to design requirements that the current state WRITE and is a function of state input WRITE_MASK. This procedure based on VHDL, development environment for MAXPLUS2 Platform: |
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Author:weixiaoyu |
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Description: 台湾人梁奕智写的VHDL编程学习的PPT讲义，里面包括内容有D触发器、寄存器、累加器、计数器、有限状态机等非常有用的内容。-Taiwanese Liang-chi written in VHDL programming learning PPT lectures, which include the contents of D flip-flops, registers, accumulators, counters, finite state machine such as a very useful content. Platform: |
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Author:WeimuMa |
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Description: This an exercise in using finite state machines.基于ALTERA的DE2开发
平台，设计一个有限状态机FSM(finite state machines).-This an exercise in using finite state machines. Based on ALTERA s DE2 development platform to design a finite state machine FSM (finite state machines). Platform: |
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Author:sopc |
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Description: 用VHDL语言将二进制数据转换成十进制数据，并将十进制的每一个位分离出来单独存放。使用状态机实现，程序简单，仿真效果很理想，占用可编程器件的资源较少。-VHDL language with the binary data into decimal data and decimal places separated from each store individually. Realize the use of state machine, the program is simple, simulation results are satisfactory, occupation of programmable devices have fewer resources. Platform: |
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Author:yato_logo |
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Description: 实现长途电话，市话的计时，还有免费电话 在verilog中用状态机实现-The achievement of long-distance calls, the city of the time, then, there are toll-free number in verilog state machine used to achieve Platform: |
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Author:邱波 |
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Description: 一个用vhdl语言写的交通灯控制的例子，可以很好的学习vhdl语言中状态机的使用。-Written in a language with vhdl traffic light control case study can be a good vhdl state machine language to use. Platform: |
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Author:tofly |
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Description: 状态机的VHDL实现，在quartus-ii7.2上测试通过，文件包括米利状态机，摩尔状态机，ADC0809的状态机实现，序列检测器和定时去毛刺的状态机实现。-State machine code in VHDL,successfully tested in quartus-ii7.2,the file contains mealy state machine,moore state machine,ADC 0809 and sequence detector achieved in state machine. Platform: |
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Author:baoguocheng |
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