Description: Stereo-Vision circuit description, Aug 2002,
Ahmad Darabiha
This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and
sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the
sub-circuits can be used as smaller benchmarks. Platform: |
Size: 420864 |
Author:junsung |
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