Search - stopwatch FPGA

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[VHDL-FPGA-Verilog] EDA_clock1 DL : 0: 电子秒表电路，可在开发版上下载运行，verlog开发-electronic stopwatch circuit may download the development version running verlog Development
Update : 2025-02-17 Size : 3.24mb Publisher : 李佳丽
[VHDL-FPGA-Verilog] FPGAdigitaltimer DL : 0: 本设计要实现一个具有预置数的数字钟的设计,具体要求如下: 1. 正确显示年、月、日 2. 正确显示时、分、秒 3. 具有校时,整点报时和秒表功能 4. 进行系统模拟仿真和下载编程实验,验证系统的正确性 -designed to achieve this with a number of preset clock design, and specific requirements are as follows : 1. Display correctly, , 2. display correctly when, minutes and 3 seconds. with school, the whole point timekeeping and stopwatch functions 4. for system simulation and download programming an experiment to test the correctness of system
Update : 2025-02-17 Size : 491kb Publisher : wangpeng
[VHDL-FPGA-Verilog] kevin_timer DL : 0: FPGA 上的数字秒表及完整的显示功能。-FPGA digital stopwatch and complete display.
Update : 2025-02-17 Size : 1kb Publisher : chen
[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga DL : 0: 基于FPGA的多功能数字钟的设计与实现内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Update : 2025-02-17 Size : 3.14mb Publisher :
[VHDL-FPGA-Verilog] VHDL_MIAOBIAO_CODE DL : 0: 基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码-CYCLONE series based on the FPGA EP1C3T144C8 stopwatch VHDL code
Update : 2025-02-17 Size : 413kb Publisher : 沈世荣
[VHDL-FPGA-Verilog] stopwatch DL : 0: 基于fpga的停表设计vudl编写，使用vhdl编写的.v文件。-the stopwatch based on fpga written with vhdl
Update : 2025-02-17 Size : 1kb Publisher : youngbing
[VHDL-FPGA-Verilog] second DL : 0: 基于FPGA的秒表设计基于FPGA的秒表设计-FPGA-based FPGA design is based on the stopwatch stopwatch stopwatch design FPGA-based design
Update : 2025-02-17 Size : 467kb Publisher : shmyg
[VHDL-FPGA-Verilog] paobiao DL : 1: 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
Update : 2025-02-17 Size : 43kb Publisher : jyb
[VHDL-FPGA-Verilog] stopwatch DL : 0: Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
Update : 2025-02-17 Size : 454kb Publisher : kg21kg
[VHDL-FPGA-Verilog] stopwatch DL : 0: The program is written in verilog to accomplish functions of a stopwatch. It can be implemented in Xilinx FPGA spartan 3 board.
Update : 2025-02-17 Size : 2kb Publisher : flyingwings
[VHDL-FPGA-Verilog] STOPWATCH DL : 0: 是基于FPGA/CPLD的跑表程序，可以存储记录多个运动员的跑步时间，是利用VHDL语言编写的，可以有助于学习EDA技术，可以参考学习，可以帮助你完成VHDL语言的课程设计。-Is based on FPGA/CPLD s stopwatch program, many athletes can store records of running time, is the use of VHDL language, and can help to learn EDA, can refer to the study, can help you complete VHDL language curriculum design.
Update : 2025-02-17 Size : 646kb Publisher : 王亮
[VHDL-FPGA-Verilog] code DL : 0: 这是一个数字跑表的代码，用FPGA实现的，对大家或许有用-This is a digital stopwatch in the code, FPGA implementation, perhaps all of us
Update : 2025-02-17 Size : 158kb Publisher : 马秀成
[VHDL-FPGA-Verilog] 6.1 DL : 0: FPGA实现多功能闹钟，有电子钟、秒表、定时器、电子琴功能-FPGA realization of multi-function alarm clock, which can function as a clock, a stopwatch, a timer,and a piano.
Update : 2025-02-17 Size : 1.59mb Publisher : f
[VHDL-FPGA-Verilog] stopwatch DL : 0: 基于FPGA用VERILOG编写的一个跑表程序....可以实现四位计数跑表-FPGA-based preparation of a stopwatch with a VERILOG program .... can achieve four counts stopwatch ...
Update : 2025-02-17 Size : 322kb Publisher : 王子辰
[VHDL-FPGA-Verilog] Stopwatch DL : 0: Stop-watch for FPGA on 7 segment display
Update : 2025-02-17 Size : 6kb Publisher : Aida
[VHDL-FPGA-Verilog] vhdl-dianziwannianli DL : 0: 基于FPGA的电子万年历，此电子万年历系统主要有8个模块分别设计1. 主控制模块 maincontrol 2. 时间及其设置模块 timepiece_main 3. 时间显示动态位选模块 time_disp_select 4. 显示模块 disp_data_mux 5. 秒表模块 stopwatch 6. 日期显示与设置模块 date_main 7. 闹钟模块 alarmclock 8. 分频模块 fdiv -FPGA-based electronic calendar, the electronic calendar system, there are 8 modules are designed for 1. The main control module maincontrol 2. Time and the setup module timepiece_main 3. Time Choice module displays dynamic time_disp_select 4. Display Module disp_data_mux 5. Stopwatch module stopwatch 6. Date display and set the module date_main 7. alarm module alarmclock 8. fdiv frequency module
Update : 2025-02-17 Size : 1kb Publisher : 黄枫
[VHDL-FPGA-Verilog] electronic-clock DL : 0: Verliog HDL数字系统设计项目，电子钟。该电子钟可以实现时钟、日期、闹钟、秒表功能。-Verliog HDL digital system design projects, electronic clock. The clock can clock, date, alarm clock, stopwatch function.
Update : 2025-02-17 Size : 1.87mb Publisher : saln
[VHDL-FPGA-Verilog] FPGA-clock DL : 0: 用FPGA编写程序实现数字时钟的设计，具有计时、秒表及闹钟功能-FPGA programming with digital clock design, with timing, stopwatch and alarm functions
Update : 2025-02-17 Size : 149kb Publisher : min
[VHDL-FPGA-Verilog] stopwatch DL : 0: 在fpga上实现秒表计数器的设计，主要目的是实现对fpga基本的认识-Stopwatch counter on the fpga design, the main aim is to achieve understanding of the basic fpga
Update : 2025-02-17 Size : 1kb Publisher : houxiaoshuai
[VHDL-FPGA-Verilog] STOPWATCH DL : 0: STOPWATCH FPGA SEVEN SEGMENT DISPLAY
Update : 2025-02-17 Size : 377kb Publisher : ramaseshu

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