Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - stopwatch by verilog

Search list

[Embeded-SCM Develop] paobiao

Description: 用verilog写的跑表程序--Stopwatch program written by verilog.
Platform: | Size: 951 | Author: 李兵 | Hits:

[Embeded-SCM Develop] paobiao

Description: 用verilog写的跑表程序--Stopwatch program written by verilog.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] secondwatch

Description: 用VERILOG实现的秒表 用VERILOG实现的秒表-Realized by Verilog Verilog achieved using a stopwatch stopwatch
Platform: | Size: 393216 | Author: wwyjs163 | Hits:

[VHDL-FPGA-Verilog] StopWatch

Description: Verilog 编写的 秒表程序，在数码管上显示，带有清0和暂停键-Stopwatch Implemented by Verilog hdl
Platform: | Size: 584704 | Author: 洪磊 | Hits:

[VHDL-FPGA-Verilog] watch

Description: 基于verilog-HDL的电子秒表电路，采用quartusII72编译仿真，经下载测试通过。-Verilog-HDL-based electronic stopwatch circuit simulation using quartusII72 compiled by downloading the test.
Platform: | Size: 388096 | Author: 潘萌 | Hits:

[Other] verilog

Description: 设计可以对两个运动员赛跑计时的秒表:(1）只有时钟（clk）和一个按键（key），每按一次，key是持续一个时钟周期的高电平脉冲 （2）秒表输出用0－59的整数表示 （3）key： （A）按一下key，开始计数； （B）第一个运动员到终点时第二下key，记住时间，继续计数； （C）二个运动员到时按第三下key，停止计数； （D）然后按第四下key，秒表输出第一个运动员到终点的时间，即按第二下key时记住的计数值； （E）按第五下key，秒表清0。 -Design of the two athletes running time of the stopwatch: (1) Only the clock (clk) and a button (key), each time, key is continuing a clock cycle, high pulse (2) stopwatch output with 0-59 integer that (3) key: (A) Click the key, start counting (B) When the first player to finish under the second key, remember the time, continue to count (C) two players to press the third Under the key, stop counting (D) and then by the fourth under the key, stopwatch output of the first athletes to the end of the time, that is, the next key by the second count when remembered (E) by the fifth under the key, stopwatch clear 0.
Platform: | Size: 1024 | Author: gab | Hits:

[VHDL-FPGA-Verilog] watch

Description: verilog 完全集合了电子表所拥有的功能，计时，调时，秒表，闹钟四个功能-verilog completely owned by a collection of spreadsheet functions, timing, tone, the stopwatch, alarm clock features four
Platform: | Size: 1516544 | Author: 孙祥龙 | Hits:

[VHDL-FPGA-Verilog] stopwatch-by-verilog-HDL

Description: 一个基于FPGA用verilog HDL 编写的数字秒表已经LED灯的配合-LED lamp with a digital stopwatch has been prepared based on the FPGA using verilog HDL
Platform: | Size: 807936 | Author: 李博 | Hits:

[VHDL-FPGA-Verilog] Timer

Description: Verilog编写的多功能秒表，Quartus仿真及硬件测试通过。-Verilog prepared by the multi-function stopwatch, Quartus simulation and hardware testing through.
Platform: | Size: 1686528 | Author: styx | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 由verilog编写的秒表程序，按键控制 按下一键秒表停止 按下另外一键 秒表又运行-Verilog prepared by a stopwatch program, press a button control key pressed another button to stop the stopwatch stopwatch and run
Platform: | Size: 814080 | Author: lida | Hits:

[VHDL-FPGA-Verilog] clock_display

Description: 自己用verilog语言编写的数字钟程序，能在Alter公司的DE0板上完美运行，能时间计时，日期，闹钟，秒表的功能。 欢迎交流学习。-The digital clock program which developed by verilog language can run at Alter DE0 board, to the time time, date, alarm clock, stopwatch function.
Platform: | Size: 3161088 | Author: 黄杰 | Hits:

CodeBus www.codebus.net