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[VHDL-FPGA-Verilog] add_sub_lab2

Description: 实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.
Platform: | Size: 60416 | Author: 徐轶尊 | Hits:

[VHDL-FPGA-Verilog] fpu

Description: 使用VHDL语言描述的单精度浮点处理器。源代码来自国外网站。可实现单精度浮点数的加减乘运算。-Described in VHDL language using single-precision floating-point processor. Web site source code from abroad. Can be achieved single precision floating point addition and subtraction, multiplication.
Platform: | Size: 16384 | Author: WeimuMa | Hits:

[VHDL-FPGA-Verilog] divide

Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
Platform: | Size: 1024 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] alu

Description: 4位ALU逻辑运算单元，可进行加法、减法、逻辑运算、移位等操作。-4 ALU logical operation unit, can be additive, subtraction, logic operations, shift and other operations.
Platform: | Size: 1024 | Author: 甲天下 | Hits:

[VHDL-FPGA-Verilog] 8_jjfq

Description: 用VHADL和Verilog HDL实现带进位的8位加减法器。-Using Verilog HDL and realize VHADL into 8-bit instruments used in addition and subtraction.
Platform: | Size: 2048 | Author: 赵文武 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ALU

Description: ALU可以实现16种操作（包括加减乘除移位运算等）-ALU can be 16 kinds of operations (including addition and subtraction multiplication and division shift operator, etc.)
Platform: | Size: 838656 | Author: 草野彰 | Hits:

[VHDL-FPGA-Verilog] addersubtractor

Description: 可以实现加法和减法的VHDL源码，可以在FPGA上运行-Addition and subtraction can realize the VHDL source code can be run in FPGA
Platform: | Size: 1024 | Author: chen | Hits:

[VHDL-FPGA-Verilog] post_norm_addsub

Description: 浮点加减运算的后规格化VHDL程序源代码，很不错，希望对大家有用-Floating-point addition and subtraction operations after the standardized VHDL source code, it is good, I hope all of you a useful
Platform: | Size: 3072 | Author: zhshup | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 在Xilinx7.1平台下编写的ALU代码，可以实现五位加法、减法、与、异或四种运算！-Xilinx7.1 platform in the preparation of the ALU code, can be achieved five adder, subtraction, and, four computing XOR!
Platform: | Size: 1024 | Author: 梁晓炬 | Hits:

[VHDL-FPGA-Verilog] shukongfenpin

Description: 数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成 果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用 并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。-NC divider output signal frequency is a function of input data. Using traditional methods of design, process and circuit design are complex and can modify the design of the results are poor and portability. NC VHDL divider based on the design, the whole process simple, fast, easy to modify, strong portability. He can use preset number of parallel addition and subtraction counter counter to achieve. Widely used in electronic equipment, musical instruments and other digital electronic systems.
Platform: | Size: 174080 | Author: 邱颖 | Hits:

[source in ebook] VHDL

Description: VHDL对各种电路的基本实现，包括乘法器，触发器，加减法器等-VHDL for the basic realization of the various circuits, including multipliers, flip-flops, and other instruments used in addition and subtraction
Platform: | Size: 1138688 | Author: Michael | Hits:

[SCM] alu_final

Description: This a program which performs addition,subtraction,multiplication and division of two 4 bit binary numbers..therefore it is called as 4 bit binary ALU..if u have any doubt,then mail me at prem_bombay@yahoo.co.in -This is a program which performs addition,subtraction,multiplication and division of two 4 bit binary numbers..therefore it is called as 4 bit binary ALU..if u have any doubt,then mail me at prem_bombay@yahoo.co.in
Platform: | Size: 1024 | Author: SUMIT | Hits:

[VHDL-FPGA-Verilog] test4adder

Description: 用VHDL实现的加法器，可以进行减法运算，运算结果通过数码管显示，由于设计时的按键较少，所以运算的范围比较小，只能计算64以内的加减法运算，可以作为学习资料来参考。-Adder using VHDL implementation can be carried out subtraction, calculation resulted in the adoption of digital tube display, due to the design of the keys relatively small scope of operations is relatively small, only 64 less than the calculation method of addition and subtraction operations can be used as learning materials for reference .
Platform: | Size: 1573888 | Author: 周峰 | Hits:

[VHDL-FPGA-Verilog] edacounter

Description: 用VHDL语言编写的计数器，在板子上运行成功，可以循环计数，加减计数，先置数后计数等-Counter with the VHDL language, in the board to run successfully, you can cycle counting, addition and subtraction counting, numbers, counting the first home
Platform: | Size: 1069056 | Author: fana | Hits:

[ELanguage] Controlinstrumentsusedinadditionandsubtraction

Description: 应用VHDL语言设计可控加减法器单元的程序-Application of VHDL language design control procedures for addition and subtraction instruments used in cell
Platform: | Size: 4096 | Author: zxy | Hits:

[Software Engineering] DesignofFloatingPointCalculatorBasedonFPGA

Description: 给出系统的整体框架设计和各模块的实现，包括芯片的选择、各模块之间的时序以及控制、每个运算模块详细的工作原理和算法设计流程；通过VHDL语言编程来实现浮点数的加减、乘除和开方等基本运算功能；在Xilinx ISE环境下，对系统的主要模块进行开发设计及功能仿真，验证 了基于FPGA的浮点运算。 -The overall framework of system design and realization of each module which contain selection of chip，timing and control between modules，detailed principle and design process of algorithm for each module were all described；The basic calculating functions of floating-point numbers，such as addition, subtraction，multiplication，division and extraction were implemented with VHDL. In the circumstance of Xilinx ISE，the development and functional simulation for main modules of system were accomplished，and then floating point calculation based on FPGA Was confirmed
Platform: | Size: 3488768 | Author: mabeibei | Hits:

[assembly language] cpu

Description: vhdl编的cpu，自己的课程验收实验，微指令实现，流程详细。存储，加减基本运算均有，乘法使用位移相加法得到。其中excel有微程序控制信号的编码，储存ram编写，控制器rom编写等-vhdl code of cpu, its acceptance test program, microcode implementation process in detail. Storage, addition and subtraction are the basic operations, multiplication by using displacement additive method. A micro-program control signal which excel coding, storage ram write, write and so the controller rom
Platform: | Size: 2267136 | Author: 林云龙 | Hits:

[Other] test

Description: 简易计算器 2位数字的加减乘除 用VHDL编程 在实验箱上实现-Simple Calculator 2-digit addition and subtraction, multiplication and division using VHDL programming to achieve in the experimental box
Platform: | Size: 3794944 | Author: 方婷 | Hits:

[Other] qdq

Description: l、设计用于竞赛的四人抢答器，功能如下： (1) 有多路抢答器，台数为四； (2) 具有抢答开始后20秒倒计时，20秒倒计时后无人抢答显示超时，并报警； (3) 能显示超前抢答台号并显示犯规警报； (4) 能显示各路得分，并具有加、减分功能； 2、系统复位后进入抢答状态，当有一路抢答键按下 [qingdaqi.rar] - 四路抢答器，超时报警，提前抢答报警，计分等 -l, designed for race four Responder, functions as follows: (1) a number of road Responder, Taiwan, the number is four (2) has the answer in 20 seconds after the beginning of the countdown, 20 seconds after the countdown show no answer in overtime, and alarm (3) can show answer in advance and display the foul alarm station number (4) to display scores from various quarters, and with addition, subtraction, sub-functions 2, enter the answer in the state after a system reset, when a key is pressed all the way Responder [qingdaqi.rar]- Quad Responder, time-out alarm, alarm answer in advance, namely, classification
Platform: | Size: 2048 | Author: 杰克 | Hits:

[VHDL-FPGA-Verilog] alu

Description: This 8 bit unsigned arithematic logical unit(ALU). This code is developed in VHDL language and compatible with any VHDL softeware like xilinx,quartus. This ALU performs addition,subtraction,multiplication,and,or,and not and pass input functions.-This is 8 bit unsigned arithematic logical unit(ALU). This code is developed in VHDL language and compatible with any VHDL softeware like xilinx,quartus. This ALU performs addition,subtraction,multiplication,and,or,and not and pass input functions.
Platform: | Size: 94208 | Author: chunduru | Hits:
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