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[Other resource] suoxianghuan DL : 0: 用凌阳单片机输入频率控制并输出14位2进制码锁住相应频率
Update : 2008-10-13 Size : 7.07kb Publisher : 李博
[Other resource] suoxianghuan DL : 0: 使用XILINX的FPGA进行简单的倍频
Update : 2008-10-13 Size : 4.32kb Publisher : toneytang
[Other resource] suoxianghuan DL : 0: 锁相环的仿真以及含有文本，希望能有帮助。锁相环对通信中还是很重要的
Update : 2008-10-13 Size : 685.01kb Publisher : 蔡立凤
[Other resource] suoxianghuan DL : 0: 常用的锁相环技术，此程序是我在设计高频电路中运用的，具体见程序，经调试无问题
Update : 2008-10-13 Size : 2.55kb Publisher : 马新文
[SCM] suoxianghuan DL : 0: 用凌阳单片机输入频率控制并输出14位2进制码锁住相应频率-With Sunplus Singlechip frequency control input and output 14 2 hexadecimal code corresponding frequency locked
Update : 2025-02-17 Size : 58kb Publisher : 李博
[VHDL-FPGA-Verilog] suoxianghuan DL : 0: 使用XILINX的FPGA进行简单的倍频
Update : 2025-02-17 Size : 4kb Publisher : toneytang
[VHDL-FPGA-Verilog] suoxianghuan DL : 0: 锁相环的仿真以及含有文本，希望能有帮助。锁相环对通信中还是很重要的-Phase-Locked Loop Simulation as well as containing text, hoping to have help. Phase-locked loop of communication is very important
Update : 2025-02-17 Size : 685kb Publisher : 蔡立凤
[VHDL-FPGA-Verilog] suoxianghuan DL : 0: 常用的锁相环技术，此程序是我在设计高频电路中运用的，具体见程序，经调试无问题-Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging
Update : 2025-02-17 Size : 2kb Publisher : 马新文
[Documents] suoxianghuan DL : 0: 在数据采集系统中，锁相环是一种非常有用的同步技术，因为通过锁相环，可以使得不同的数据采集板卡共享同一个采样时钟。-In the data acquisition system, the phase-locked loop is a very useful synchronization technology, because the adoption of phase-locked loop, you can make the different data acquisition boards share the same sampling clock.
Update : 2025-02-17 Size : 1kb Publisher : hellen
[SCM] suoxianghuan DL : 0: 此为锁相环函数发生器包括键盘扫描程序频率显示程序波形显示程序-This is the phase-locked function generators including the keyboard scanner frequency waveform display shows process procedures, etc.
Update : 2025-02-17 Size : 3kb Publisher : 王华
[matlab] suoxianghuan DL : 0: 锁相环（PLL）simulink仿真，加深对PLL的理解-Phase-locked loop (PLL) simulink simulation, to deepen understanding of the PLL
Update : 2025-02-17 Size : 146kb Publisher : ZLJ
[VHDL-FPGA-Verilog] suoxianghuan DL : 0: 这是一款计算锁相环参数的软件，附有源程序-This is a phase-locked loop parameters for the calculation software, with source code
Update : 2025-02-17 Size : 849kb Publisher : 刘溶
[Other] suoxianghuan DL : 0: 锁相环电路原理及其应用，对从事电路设计人员有很大帮助-suoxianghuandianlu
Update : 2025-02-17 Size : 4.29mb Publisher : fuqiang
[Other] suoxianghuan DL : 0: 基于锁相环的频率合成器的设计
Update : 2025-02-17 Size : 89kb Publisher :
[Linux-Unix] suoxianghuan DL : 0: 1.了解锁相环的工作原理。 2、学习使用Cyclone器件中的嵌入式锁相环。 3、掌握数字存储示波器的使用方法。 4、测试嵌入式锁相环输出信号的特性。 -1. To understand the working principle of phase-locked loop. 2, learning to use Cyclone devices in the embedded phase-locked loop. 3, the digital storage oscilloscope is used. 4, testing embedded phase-locked loop output signal characteristics.
Update : 2025-02-17 Size : 27kb Publisher : shanxu
[Special Effects] suoxianghuan DL : 0: 实现所想换实现所想换实现所想换 -shi xian suo xiang haun bie luo suo be a good help shi xian suo xiang haun bie luo suo be a good helpshi xian suo xiang haun bie luo suo be a good help shi xian suo xiang haun bie luo suo be a good helpshi xian suo xiang haun bie luo suo be a good help shi xian suo xiang haun bie luo suo be a good help
Update : 2025-02-17 Size : 1kb Publisher : yufeimen3
[VHDL-FPGA-Verilog] suoxianghuan DL : 0: fpja的锁相环，我自己当时也没有做到完全锁相，可以给其他同学们作一个参考，-fpjade suoxianghuan
Update : 2025-02-17 Size : 346kb Publisher : weibiaohua
[Communication-Mobile] suoxianghuan DL : 0: 通信系统中锁相环的实现及其原理,同过matlab编程实现-communication system and PLL relazition
Update : 2025-02-17 Size : 5kb Publisher : 陈鹏
[Other] suoxianghuan DL : 0: 锁相环仿真设计，基本的原理实现，给大家参考一下-Phase-locked loop simulation design, the basic principle to achieve for your reference
Update : 2025-02-17 Size : 2kb Publisher : jljlg
[Other] suoxianghuan DL : 0: 锁相环模型，可以用于很多种控制中，应用很普遍-PLL model, can be used for very many kinds of control, the application is very common
Update : 2025-02-17 Size : 6kb Publisher : gonglin

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