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[VHDL-FPGA-Verilog] anjian DL : 0: 按键输入模块（key）： --可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型 --前端模块：消抖 --对i0－i9十个输入端的两点要求： --（1）输入端要保证一段时间的稳定高电平 --（2）不能同时按下两个或多于两个的键 --后级模块：1、编码；2、可变模计数器 --编码模块：8线－4线（0－8 BCD码） --可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) :-- programmable delay generator (digital synchronous machine) the front-end input module : 0-2-9 10 numeric keys keys input module prototype-- front-end module : Consumers quiver-- the domain-Makes 10 input of the two requirements :-- (a) input to ensure a period of stability to I-- (2) can not be pressed together two or more two keys-- after class modules : one, coding; 2, variable Die counter-- Coding modules : 8-to-four (0-8 BCD)-- Variable Mode counter modules : coding module output to the 32 BCD value to Die
Update : 2025-02-17 Size : 2kb Publisher : 汪汪
[Other Embeded program] GE15 DL : 0: 同步发电机同步电动机软启动电子开关通用的晶砸管控制程序.-synchronous generator synchronous motor soft-start electronic switch generic crystal smashing control procedures.
Update : 2025-02-17 Size : 22kb Publisher : 曾敏
[Algorithm] ztwd DL : 0: 电力系统在台稳定计算式电力系统不正常运行方式的一种计算。它的任务是已知电力系统某一正常运行状态和受到某种扰动，计算电力系统所有发电机能否同步运行 1运行说明：请输入初始功率S0，形如a+bi 请输入无限大系统母线电压V0 请输入系统等值电抗矩阵B 矩阵B有以下元素组成的行矩阵 1正常运行时的系统直轴等值电抗Xd 2故障运行时的系统直轴等值电抗X d 3故障切除后的系统直轴等值电抗请输入惯性时间常数Tj 请输入时段数N 请输入哪个时段发生故障Ni 请输入每时段间隔的时间dt-power system stability in the Taiwan Power computing system is not the normal operating mode of calculation. Its mission is a known power system uptime status and be subject to some disturbance, computing power system all synchronous generator can run an operation Note : Please enter the initial power S0, shaped like a bi Please enter the infinite system bus voltage V0 Please enter the system equivalent reactance matrix B matrix B group has the following elements the line matrix into a normal operation of the system straight axis equivalent reactance Xd two fault systems running straight axis equivalent reactance X d 3 after resection of the fault system straight axis equivalent reactance Please enter the inertial time constant Tj Please enter the number of hours which N Please enter a tim
Update : 2025-02-17 Size : 1kb Publisher : 魏鹏
[matlab] smvecstart DL : 0: STARTING OF A SYNCHRONOUS MACHINE,MATLAB/SIMULINK 下对同步电机启动的仿真，解压同一目录下，双击下部图标进行参数运行点设置。-OF STARTING A Synchronous winreg. MATLAB/Simulink right under the synchronous motor launch simulation, extracting the same directory, double-click the icon for the lower operating parameter settings.
Update : 2025-02-17 Size : 8kb Publisher : 李健
[VHDL-FPGA-Verilog] CummingsSNUG2002SJ_Resets DL : 0: Synchronous Resets? Asynchronous Resets?I am so confused!How will I ever know which to use? 复位信号的论文-Synchronous Resets Asynchronous Resets I am so confused! How will I ever know which to use Minute Signal-paper
Update : 2025-02-17 Size : 237kb Publisher : 黄名
[VHDL-FPGA-Verilog] simple_fifo DL : 0: verilog HDL原码一种简单的同步FIFO原码，可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated
Update : 2025-02-17 Size : 1kb Publisher : zxz
[matlab] PN_synchronization_simlulink DL : 1: 基于PN序列的同步仿真链路（simulink+m files），收端算法为接受序列与本地序列求滑动相关。-PN sequence based on the synchronous Link Simulation (Simulink m files), Algorithm-admission to accept the sequence with the local demand sliding related sequences.
Update : 2025-02-17 Size : 22kb Publisher : 徐
[ELanguage] bakema DL : 0: 该程序实现了巴克码（1110010）作群同步码的识别器。-the realization of Buck code (1110010) for the group synchronous code identifier.
Update : 2025-02-17 Size : 6kb Publisher : 李家军
[VHDL-FPGA-Verilog] syn_fifo DL : 0: 同步FIFO的verilog编码 -synchronous FIFO verilog coding synchronous FIFO verilog Synchronous Code FI FOR the verilog coding synchronous FIFO verilog coding
Update : 2025-02-17 Size : 1kb Publisher :
[SCM] fifo DL : 0: 一个同步FIFO，包括testbench，-A synchronous FIFO, including the testbench,
Update : 2025-02-17 Size : 1kb Publisher : 张丰
[matlab] psbpmmotor DL : 0: 模糊控制永磁同步电机，在模糊控制器作用下，控制电机转速。-Fuzzy control of permanent magnet synchronous motor, in the fuzzy controller under the control of motor speed.
Update : 2025-02-17 Size : 8kb Publisher : wanglei
[matlab] power_svpwm DL : 1: 基于svpwm（矢量控制技术）的永磁同步电机仿真模型，在simulink里面仿真-Based on svpwm (vector control technology) simulation model of permanent magnet synchronous motor, which in simulink simulation
Update : 2025-02-17 Size : 17kb Publisher : 杨红
[Other] Some_VHDL_Examples DL : 0: 几个VHDL的例子，供大家参考，包括寄存器的设计，同步二进制计数器的设计，时钟计数器的设计等，个人觉得很有用处-Several examples of VHDL for reference, including the register of designs, synchronous binary counter design, the design of the clock counter, personal feel that is very useful
Update : 2025-02-17 Size : 165kb Publisher : 钱
[DSP program] 3phase-PMSM-Field-Oriented-Control DL : 0: 三相永磁同步伺服电动机磁场定向速度控制程序-Three-phase permanent magnet synchronous servo motor speed field-oriented control procedures
Update : 2025-02-17 Size : 27kb Publisher : 江可乐
[matlab] PMSG_test_w DL : 0: 永磁同步发电机控制，自建的永磁同步发电机模型，可接感性负载。-Permanent magnet synchronous generator control, self-built permanent magnet synchronous generator model, which can be accessed by inductive load.
Update : 2025-02-17 Size : 16kb Publisher : cml
[File Format] Synchronous DL : 0: Update : 2025-02-17 Size : 9kb Publisher : chuchu
[VHDL-FPGA-Verilog] binarycount DL : 0: 异步复位、同步置数的四位二进制计数器的VHDL源文件-Asynchronous reset, synchronous purchase the number of binary counter 4 of the VHDL source files
Update : 2025-02-17 Size : 1kb Publisher : chenwen
[Communication] OPC DL : 0: OPC客户端开发必看,这是包含多个源码,同步,异步通讯的都有.-OPC client development a must-see, it is contains more than one source, synchronous, asynchronous communications are.
Update : 2025-02-17 Size : 618kb Publisher : hou
[Other] Synchronous DL : 1: 详细讲解了同步原理，包括载波同步、位同步、帧同步-Detailed account of the principle of synchronization, including the carrier synchronization, bit synchronization, frame synchronization
Update : 2025-02-17 Size : 300kb Publisher : wuqianye
[Other] syn_fifo DL : 0: Synchronous FIFO 用來處理synchronous clock domains間的傳輸-Synchronous FIFO for handling synchronous clock domains between the transmission
Update : 2025-02-17 Size : 2kb Publisher : 洪銘澤

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