Description: 按键输入模块（key）：
--可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型
--前端模块：消抖
--对i0－i9十个输入端的两点要求：
--（1）输入端要保证一段时间的稳定高电平
--（2）不能同时按下两个或多于两个的键
--后级模块：1、编码；2、可变模计数器
--编码模块：8线－4线（0－8 BCD码）
--可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) :-- programmable delay generator (digital synchronous machine) the front-end input module : 0-2-9 10 numeric keys keys input module prototype-- front-end module : Consumers quiver-- the domain-Makes 10 input of the two requirements :-- (a) input to ensure a period of stability to I-- (2) can not be pressed together two or more two keys-- after class modules : one, coding; 2, variable Die counter-- Coding modules : 8-to-four (0-8 BCD)-- Variable Mode counter modules : coding module output to the 32 BCD value to Die Platform: |
Size: 2048 |
Author:汪汪 |
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Description: 基于fpga和sopc的用VHDL语言编写的EDA含异步清0和同步时钟使能的加法计数器-FPGA and SOPC based on the use of VHDL language with asynchronous EDA-ching 0 and synchronous clock so that the adder counter Platform: |
Size: 34816 |
Author:多幅撒 |
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Description: 几个VHDL的例子，供大家参考，包括寄存器的设计，同步二进制计数器的设计，时钟计数器的设计等，个人觉得很有用处-Several examples of VHDL for reference, including the register of designs, synchronous binary counter design, the design of the clock counter, personal feel that is very useful Platform: |
Size: 168960 |
Author:钱 |
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Description: 异步复位、同步置数的四位二进制计数器的VHDL源文件-Asynchronous reset, synchronous purchase the number of binary counter 4 of the VHDL source files Platform: |
Size: 1024 |
Author:chenwen |
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Description: 这是同步十进制计数器的源程序，有需要的同学可以参照一下！-This is a source synchronous decimal counter, needy students can refer to you! Platform: |
Size: 33792 |
Author:逗号 |
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Description: 数字频率计的设计可以分为测量计数和显示。其测量的基本原理是计算一定时间内待测信号的脉冲个数，这就要求由分频器产生标准闸门时间信号，计数器记录脉冲个数，由控制器对闸门信号进行选择，并对计数器使能断进行同步控制。控制器根据闸门信号确定最佳量程。-The design of digital frequency meter can be divided into measurement and display count. The basic principle of its measurement is calculated under test signal within a certain period of time the number of pulses, which have a standard requirement by the divider gate time signal pulse counter records the number of signals from the controller to choose the gates and counters to make off synchronous control can be carried out.Controller based on the gate signal to determine the optimum range. Platform: |
Size: 54272 |
Author:黄花 |
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Description: Ripple Carry Counter. the synchronous version of Ripple Counter. a bit less fasr version the ripple counter but a synchronmous one that will work well on FPGA. wrriten in behavioral VHDL. Platform: |
Size: 20480 |
Author:avi |
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Description: vhdl,无进位同步计数器，完成6进制加，输出6进制序列数-vhdl, non-binary synchronous counter to complete the six binary Canada, output 6, the number of binary sequences Platform: |
Size: 37888 |
Author:王晓虎 |
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Description: 第一章到第五章的代码
本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation. Platform: |
Size: 1580032 |
Author:xiao |
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Description: 第六章到第九章的代码
本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation. Platform: |
Size: 6281216 |
Author:xiao |
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Description: 第十一章到第十三章的代码
本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation. Platform: |
Size: 5088256 |
Author:xiao |
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Description: Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts down otherwise, it counts up. The counter should have asynchronous set input to set the count to your last two digits of your student ID, synchronous clear input to clear the count to 0, and enable input to enable counting. Set input has higher priority than the clear input. For now, you may assume that the clock to the counter is a 1 Hz clock. For subsequent homework, you need to design a circuit that generates the 1 Hz clock signal from the 50 MHz system clock.-Count starts from 78 down to 56, back to 78, counts down to 56, and repeat. If the counter is cleared, count starts from 0 up to 78 and then counts down to 56, back to 78, and repeat. If the counter is set, the count sets to 78. The counter will not count when it is disabled. Platform: |
Size: 295936 |
Author:XingSu |
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Description: 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features:
The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered.
The counter is with an asynchronous reset that assigns a specific initial value for counting.
The counter is with a synchronous data load control input for a new value of counting and an enable control input for allowing the up and down counting. The load control input has a priority over the enable control input. This implies that when the load operation is in process the counter operation is prohibited.
Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER, may be used. Platform: |
Size: 1024 |
Author:fjmwu |
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Description: 用 vhdl 设计含异步清零和同步时钟使能的十进制加法计数器。再用 vhdl 设计含异步清零和同步时钟使能的十进制加减可控计数器。
-With vhdl design with asynchronous clear and synchronous clock enable decimal up counter. Vhdl design and then synchronize with asynchronous clear and clock enable control counter decimal addition and subtraction. Platform: |
Size: 1024 |
Author:釉雪Dreamer |
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Description: 8位上下同步计数器 适宜小型练手操作 易于理解(an 8-bit up and down synchronous counter in VHDL with the following
features:
(1) The same ports are used for signals to be inputted and outputted. The ports are
bi-directionally buffered (three-state).
(2) The counter is with an asynchronous reset that assigns a specific initial value
for counting.
(3) The counter is with a synchronous data load control input for a new value of
counting and an enable control input for allowing the up and down counting.
The load control input has a priority over the enable control input. This
implies that when the load operation is in process the counter operation is
prohibited.
(4) Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER,
may be used) Platform: |
Size: 1014784 |
Author:名之联 |
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Search - synchronous counter vhdl