Search - tap Verilog

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[Other resource] jtag DL : 0: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证
Update : 2008-10-13 Size : 621.36kb Publisher : hegs
[Other resource] BiDirectionalCell DL : 0: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证
Update : 2008-10-13 Size : 1kb Publisher : hegs
[Other resource] ControlCell DL : 0: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证
Update : 2008-10-13 Size : 1.31kb Publisher : hegs
[Other resource] InputCell DL : 0: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证
Update : 2008-10-13 Size : 1.16kb Publisher : hegs
[Other resource] OutputCell DL : 0: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证
Update : 2008-10-13 Size : 1.38kb Publisher : hegs
[VHDL-FPGA-Verilog] fir DL : 0: 完成一个FIR数字滤波器的设计。要求： 1、基于直接型和分布式两种算法。 2、输入数据宽度为8位，输出数据宽度为16位。 3、滤波器的阶数为16阶，抽头系数分别为h[0]=h[15]=0000，h[1]=h[14]=0065，h[2]=h[13]=018F，h[3]=h[12]=035A，h[4]=h[11]=0579，h[5]=h[10]=078E，h[6]=h[9]=0935，h[7]=h[8]=0A1F。 -Completion of a FIR digital filter design. Requirements: one, based on the direct type and distributed two algorithms. 2, input data width of 8, the output data width of 16. 3, filter order of 16 bands, tap coefficients for h [0] = h [15] = 0000, h [1] = h [14] = 0065, h [2] = h [13] = 018F , h [3] = h [12] = 035A, h [4] = h [11] = 0579, h [5] = h [10] = 078E, h [6] = h [9] = 0935, h [7] = h [8] = 0A1F.
Update : 2025-02-17 Size : 5kb Publisher : fredyu
[VHDL-FPGA-Verilog] jtag DL : 0: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Update : 2025-02-17 Size : 621kb Publisher : hegs
[VHDL-FPGA-Verilog] BiDirectionalCell DL : 0: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Update : 2025-02-17 Size : 1kb Publisher : hegs
[VHDL-FPGA-Verilog] ControlCell DL : 0: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Update : 2025-02-17 Size : 1kb Publisher : hegs
[VHDL-FPGA-Verilog] OutputCell DL : 0: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证
Update : 2025-02-17 Size : 1kb Publisher : hegs
[Other] JTAG-TAP DL : 0: JTAG TAP controller verilog source code
Update : 2025-02-17 Size : 5kb Publisher : kdlee
[Other] c73a2ceb-09a5-4366-83ea-78b08c6200eb DL : 0: jtag TAP控制状态机代码 verilog VHDL-jtag TAP state machine code
Update : 2025-02-17 Size : 2kb Publisher : 张涛
[VHDL-FPGA-Verilog] fir DL : 0: 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
Update : 2025-02-17 Size : 344kb Publisher : hongwan
[source in ebook] IIR_Filter_8 DL : 0: verilog实现8阶的iir滤波器。对于刚学习verilog的朋友来说是一个易懂的学习资料。-verilog order to achieve the iir filter 8. For just learning verilog friend is a easy to understand learning materials.
Update : 2025-02-17 Size : 1kb Publisher : zh
[VHDL-FPGA-Verilog] TAP1 DL : 0: JTAG TAP statemachine verilog code
Update : 2025-02-17 Size : 1kb Publisher : 张超
[VHDL-FPGA-Verilog] TAP2 DL : 0: JTAG TAP Statemachine verilog code
Update : 2025-02-17 Size : 1kb Publisher : 张超
[VHDL-FPGA-Verilog] TAP4 DL : 0: JTAG TAP Statemachine verilog code
Update : 2025-02-17 Size : 1kb Publisher : 张超
[VHDL-FPGA-Verilog] matlab-and-verilog-fir4_3 DL : 0: 四抽头FIR滤波器matlab,verilog顶层，子模块，以及testbench代码-Four tap FIR filter matlab, verilog top, sub modules, as well as the testbench code
Update : 2025-02-17 Size : 8kb Publisher : 李静
[VHDL-FPGA-Verilog] JTAG_Example0_Verilog DL : 0: 一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org))
Update : 2025-02-17 Size : 377kb Publisher : ZhouGuofei
[Other] tap_controller DL : 0: JTAG tap controller, used for DFT(JTAG tap controller verilog version)
Update : 2025-02-17 Size : 1kb Publisher : borselin

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