Search - taxi-vhdl

[Other resource] 20071261091933088

Description: 出租车VHDL源码不全，但是有参考价值-taxi VHDL source incomplete, but the reference value.
Platform: | Size: 49732 | Author: w | Hits:

[Other] 200603-TAXI

Description: VB6写的用于122*32的LCD字模提取程序，可以提取各种点阵中文字体的字模。稍作改进即可适用于其他点阵液晶。本程序结构简单，起抛砖引玉之作用。-VB6 written for 122* 32 LCD Abstraction procedures, can extract all the Chinese character dot-matrix Printer. Some slight improvements can be applied to other dot-matrix LCD. The procedure is simple, play the role congregate.
Platform: | Size: 1001472 | Author: 韦峻峰 | Hits:

[Windows Mobile] TAXI

Description: Pocket PC上开发的一个针对的士的收费软件。含源代码-Pocket PC development of a taxi fares against software. With source code
Platform: | Size: 47104 | Author: sdfiwh2002 | Hits:

[transportation applications] 20071261091933088

Description: 出租车VHDL源码不全，但是有参考价值-taxi VHDL source incomplete, but the reference value.
Platform: | Size: 49152 | Author: | Hits:

[VHDL-FPGA-Verilog] taxi_counter

Description: 用VHDL编写的一个出租车计费器，起步6元计2公里，此后每半公里计0.8元，停车等待每2.5分计0.8元。通过仿真，但未下载到CPLD测试-a taxi prepared by the accounting device, starting six yuan or 2 km, then every half kilometer or 0.8 yuan, stopping to wait for every 2.5 minutes or 0.8 yuan. Through simulation, but not download to test CPLD
Platform: | Size: 242688 | Author: 尚方喆 | Hits:

[VHDL-FPGA-Verilog] taxi-vhdl

Description: 出租车计费器硬件描述语言出租车计费器 MAX+PLUS软件数字系统-Taxi billing hardware description language taxi meter MAX+ PLUS software digital systems
Platform: | Size: 48128 | Author: aneeee | Hits:

[VHDL-FPGA-Verilog] taxi

Description: 在Quatus下用VerilogHDL语言编写，实现出租车计价器功能-VerilogHDL in Quatus using language to achieve functional Taximeter
Platform: | Size: 380928 | Author: baohaitao | Hits:

[SCM] Taxi

Description: 接受里程传感器的脉冲输入（在本方案中使用PWM模拟替代传感器脉冲），并对脉冲进行计量，继而转换成里程； 􀂋 采用现行出租车计价系统的计算方法，对行驶里程进行计费； 􀂋 提供友好的用户界面，并具有语音提示功能。基于凌阳单片机！-Accept the mileage sensor pulse input (in this program using alternative sensors analog PWM pulse), and pulse measuring, and then converted into mileage
Platform: | Size: 560128 | Author: 冯旭升 | Hits:

[VHDL-FPGA-Verilog] taxi

Description: VHDL开发环境，出租车计费系统，实现起步10元，每增加一公里，自动上涨2元。-VHDL development environment, taxi billing system to achieve the initial 10 yuan for each additional mile, automatic up 2.
Platform: | Size: 184320 | Author: 王蕊 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: ：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。-: A Shanghai taxi meter area for example, the use of Verilog HDL language taxi meter is designed so that it will have the time display, billing and simulated taxi start, stop, reset and other functions, and set up the dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the advantages of digital logic circuits. Source by the MAX+ PLUS Ⅱ software debugging, optimization, download EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system.
Platform: | Size: 211968 | Author: mindy | Hits:

[VHDL-FPGA-Verilog] taxi

Description: 用verilog写的基于cpld的出租车计费器的源码，需要的参考一下-Use verilog to write a taxi based cpld billing device source code, need to refer to
Platform: | Size: 1282048 | Author: 许璐璐 | Hits:

[VHDL-FPGA-Verilog] taxi

Description: 出租车计费器，用以实现出租车计费的小程序，用VHDL编程实现-Taxi meter, used to achieve a small taxi billing procedures, using VHDL programming
Platform: | Size: 36864 | Author: 天空 | Hits:

[Software Engineering] taxi

Description: 介绍了出租车计费器系统的组成及工作原理，简述了在EDA平台上用单片CPLD器件构成该数字系统的设计思想和实现过程。论述了车型调整模块、计程模块、计费模块、译码动态扫描模块等的设计方法与技巧。-Introduced a taxi meter system, the composition and working principle outlined in the EDA platform, with the single-chip CPLD devices constitute the digital system design idea and implementation process. Discusses the models to adjust module, the meter module, billing module, decoding module and so dynamic scan design methods and techniques.
Platform: | Size: 153600 | Author: 蒋思 | Hits:

[Software Engineering] vhdl-TAXI

Description: 随着EDA技术的发展及大规模可编程逻辑器件CPLD／FPGA的出现，电子系统的设计技术和工具发生了巨大的变化，通过EDA技术对CPLD／FPGA编程开发产品，不仅成本低、周期短、可靠性高，而且可随时在系统中修改其逻辑功能。本文利用VHDL语言设计出租车计费系统，使其实现汽车启动、停止、暂停时计费以及预置等功能，通过设置计数电路进行路费及路程的计数，通过设计数据转换电路将路费及路程的十进制数分离成四位十进制数表示，通过设计快速扫描电路显示车费及路费，突出了其作为硬件描述语言的良好的可读性的优点。通过MAX+PLUSⅡ软件编写、调试和优化源程序，下载到特定芯片（MAX系列的EPM 7128SLC8415）后，即可应用于实际的出租车计费系统中。-ith the development of EDA technologies and large-scale programmable logic device CPLD/FPGA emergence of electronic systems design techniques and tools has undergone tremendous changes, through the EDA technology CPLD/FPGA programming product development, not only low-cost, short lead time, high reliability, but also may at any time in the system to modify its logic function. In this paper, VHDL language design taxi billing system to achieve the car to start, stop, pause, time billing and preset functions, by setting the tolls and the distance counting circuit count, through the design of data conversion circuits and the journey will be toll separated into four decimal decimal number, said a quick scan through the design of the circuit shows fares and tolls, highlighting its position as a hardware description language, the advantages of good readability. Through the MAX+ PLUS Ⅱ software development, debugging and optimizing the source code, download to a specific chip (MAX series of EP
Platform: | Size: 269312 | Author: stella | Hits:

[VHDL-FPGA-Verilog] taxi

Description: 基于VHDL出租车计价器的设计，能实现出租车载客过程的计费作用。-VHDL-based design of a taxi meter, taxi passengers can realize the process of charging effect.
Platform: | Size: 130048 | Author: 猪猪 | Hits:

[VHDL-FPGA-Verilog] Taxi

Description: EDA课程设计出租车计价器的VHDL语言设计的程序出租车计价器：5KM起计价，起始价5元，每公里1.2元；传感器输出脉冲为0.5m/个；每0.5km改变一次显示，且提前显示（只显示钱数）-EDA curriculum Taximeter the VHDL language design process Taximeter5KM from the valuationthe starting price of 5 yuan1.2 yuan per kilometersensor output pulse is 0.5m monthper 0.5km to change a display, and early show (show only the amount of money)
Platform: | Size: 164864 | Author: 李小璐 | Hits:

[VHDL-FPGA-Verilog] taxi-meter-VHDL-design

Description: 这是基于VHDL的出租车计价器设计，可以当作来参考。-This is based on the taxi meter VHDL design can be used as to reference.
Platform: | Size: 121856 | Author: 猪大 | Hits:

[VHDL-FPGA-Verilog] TAXI

Description: 收录大量的出租车计费系统设计的资料基于CPLD FPGA的设计抱过设计报告-Contains a large number of taxi billing information system design based on CPLD FPGA design report hug
Platform: | Size: 8976384 | Author: yangvan | Hits:

[VHDL-FPGA-Verilog] Meter-VHDL-code

Description: 基于FPGA的计价器系统 FPGA；VHDL语言；出租车计价器-The Meter Design Based on FPGA FPGA VHDL Language Taxi meter
Platform: | Size: 2048 | Author: myblues | Hits:

[VHDL-FPGA-Verilog] VHDL程序

Description: 利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)
Platform: | Size: 18432 | Author: 我的期待啊 | Hits:

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[Other resource] 20071261091933088

[Other] 200603-TAXI

[Windows Mobile] TAXI

[transportation applications] 20071261091933088

[VHDL-FPGA-Verilog] taxi_counter

[VHDL-FPGA-Verilog] taxi-vhdl

[VHDL-FPGA-Verilog] taxi

[SCM] Taxi

[VHDL-FPGA-Verilog] taxi

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] taxi

[VHDL-FPGA-Verilog] taxi

[Software Engineering] taxi

[Software Engineering] vhdl-TAXI

[VHDL-FPGA-Verilog] taxi

[VHDL-FPGA-Verilog] Taxi

[VHDL-FPGA-Verilog] taxi-meter-VHDL-design

[VHDL-FPGA-Verilog] TAXI

[VHDL-FPGA-Verilog] Meter-VHDL-code

[VHDL-FPGA-Verilog] VHDL程序

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