Search - testbench SPI

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[Other resource] spi_boot-rel_3_2_rev_C.tar DL : 0: spi bootloader详细资料，里面包含C代码和VHDL代码以及testbench以及相关的说明文档，有兴趣的朋友可以下来看看。
Update : 2008-10-13 Size : 188.37kb Publisher : zheng jun
[VHDL-FPGA-Verilog] I2C_HDL DL : 0: I2C bus HDL source and testbench
Update : 2025-02-17 Size : 685kb Publisher : liuKe
[VHDL-FPGA-Verilog] spi_boot-rel_3_2_rev_C.tar DL : 0: spi bootloader详细资料，里面包含C代码和VHDL代码以及testbench以及相关的说明文档，有兴趣的朋友可以下来看看。-spi bootloader detailed information, which contains C code and VHDL code and Testbench and related documentation, interested friends can see them.
Update : 2025-02-17 Size : 188kb Publisher : zheng jun
[VHDL-FPGA-Verilog] MinWinsockSpi DL : 0: verilog ADPLL file with testbench
Update : 2025-02-17 Size : 193kb Publisher : xgh
[VHDL-FPGA-Verilog] SPI_FireWall DL : 0: verilog spi file with testbench
Update : 2025-02-17 Size : 2.8mb Publisher : xgh
[Windows CE] wince+spi DL : 0: verilog vcspi file with testbench
Update : 2025-02-17 Size : 1.85mb Publisher : xgh
[VHDL-FPGA-Verilog] spi2-testbench DL : 0: test bench for spi communication
Update : 2025-02-17 Size : 1kb Publisher : Onur
[VHDL-FPGA-Verilog] spi_verilog DL : 0: SPI协议Verilog HDL程序，内含testbench 文件
Update : 2025-02-17 Size : 80kb Publisher : dsahd
[VHDL-FPGA-Verilog] SpiMaster DL : 0: This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate
Update : 2025-02-17 Size : 9kb Publisher : RutaliMulye
[VHDL-FPGA-Verilog] maxII_spi DL : 0: MAXII SPI interface with testbench
Update : 2025-02-17 Size : 461kb Publisher : xornonop
[VHDL-FPGA-Verilog] spi_master DL : 0: 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file folder,which has been tested in Modelsim6.5,you can use it in FPGA directly.
Update : 2025-02-17 Size : 3kb Publisher : 骏
[VHDL-FPGA-Verilog] spi_vmm1.2 DL : 0: VMM1.2的SPI示例代码，介绍各个验证组件的功能和用法。Verilog编写，使用VCS仿真-The example SPI testbench code of the VMM1.2
Update : 2025-02-17 Size : 1.77mb Publisher : Tianlq
[assembly language] SPI-Core_nguyen DL : 0: SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE.STD_LOGIC_1164 IEEE.NUMERIC_STD work.general_signal_processing_pkg (included) Testbench for simulation included. Core Tested on Lattice XP2 CPLD Brevia development kit and FPGAs Xilinx Spartan-3E and Altera Cyclone-4E (industrial application)
Update : 2025-02-17 Size : 17kb Publisher : AgentNguyex
[VHDL-FPGA-Verilog] ADC_AD7490 DL : 0: THIS PROJECT IMPLEMENTED ON VITERX 4 FPGA and THE COMPLETE SOURCE FILES testbench, design file UCF file are there and THIS ADC is maily configured with SPI protocol interface SPI CLK,SPI DATA, SPI LE, the SPEED OF OPERATION OF SPI CLK is 10 MHZ
Update : 2025-02-17 Size : 762kb Publisher : LEE
[VHDL-FPGA-Verilog] SPI-master-P-tb DL : 0: SPI master VHDL realisation Also contains TestBench
Update : 2025-02-17 Size : 2kb Publisher : Stan
[Other Embeded program] spi DL : 0: It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.-It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.
Update : 2025-02-17 Size : 2kb Publisher : eren
[Embeded-SCM Develop] spi slave程序 DL : 0: spi slave的verilog程序，有测试平台testbench程序，实现fpga作为salve的功能(spi slave verilog program)
Update : 2025-02-17 Size : 5kb Publisher : CARL_2018
[VHDL-FPGA-Verilog] W25Q80NE verilog Model DL : 1: SPI FLASH官方仿真模型方便modelsim testbench调试仿真(Official simulation model facilitates debugging and simulation)
Update : 2025-02-17 Size : 1.6mb Publisher : chengruiqi