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[VHDL-FPGA-Verilog] H16550_2[1].0V

Description: 专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550 ，包含完整的使用说明手册、testbench、可综合，如果被网站认可，将继续上传其余的几个更好的core。-specialized processor and peripheral interfaces famous ipcore CAST product manufacturers UART H16 550, including full use manual testbench can be integrated, if the site is approved, the rest will continue to upload a few better core.
Platform: | Size: 386048 | Author: 宋云成 | Hits:

[Com Port] UART

Description: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

[VHDL-FPGA-Verilog] UARTtransmitter

Description: UART Transmitter. VHDL code and its testbench.
Platform: | Size: 2048 | Author: mehmet | Hits:

[VHDL-FPGA-Verilog] uart-vhdl-testbench

Description: simple uart vhdl behavioural model (package) vhdl testbench example
Platform: | Size: 2048 | Author: Mark | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
Platform: | Size: 25600 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] UART_rx_tx

Description: 串口单字节自发自收程序，内含testbench-UART single-byte receive and send program in includes testbench
Platform: | Size: 5120 | Author: 张以亮 | Hits:

[VHDL-FPGA-Verilog] uart2bus_latest.tar

Description: 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
Platform: | Size: 224256 | Author: robin | Hits:

[VHDL-FPGA-Verilog] UART

Description: UART发送verilog源码，波特率115200，以及testbench源码-Send verilog source UART baud rate 115200, and testbench source
Platform: | Size: 67584 | Author: 宁馫圈 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 这是一个uart串口实现16550的实现，代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
Platform: | Size: 35840 | Author: wangli | Hits:

[MPI] uart

Description: verilog实现UART收发源码 内有testbench-the UART transceiver Source for verilog implementation With testbench
Platform: | Size: 3072 | Author: 王军 | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart veilog源码 含有testbench-uart verilog
Platform: | Size: 2048 | Author: 王维 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 这是一个串口通讯模块，从串口接收14个数据后用于计算并将计算结果从串口发送出去，里面包含testbench。-This is a serial communication module 14 the serial port to receive data used to calculate the results and sent the serial port, which contains the testbench.
Platform: | Size: 7735296 | Author: 阿力 | Hits:

[VHDL-FPGA-Verilog] uart

Description: Atmega 328 UART clone with testbench, cannot be synthesized to gates
Platform: | Size: 65536 | Author: Sam | Hits:

[VHDL-FPGA-Verilog] uart2bus_latest

Description: uart IP, including rx,tx module,and FSM control,data paser logic. including: testbench-uart IP
Platform: | Size: 277504 | Author: andrew.zhang | Hits:

[VHDL-FPGA-Verilog] UART-master

Description: UART通讯接口verilog代码实现，uart_tx子模块和uart_rx子模块，包含详细testbench-UART interface verilog code, uart_tx、uart_rx， testbench
Platform: | Size: 196608 | Author: lv | Hits:

[VHDL-FPGA-Verilog] apb_uart

Description: 带apb接口的uart,带testbench，测试过，可以使用(The uart module with apb interface)
Platform: | Size: 3072 | Author: songchao | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用Verilog实现FPGA的uart的串行通信功能，并附有testbench(The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached)
Platform: | Size: 308224 | Author: 怪了个乖 | Hits:

[Other] apb_uart_sv-pulpinov1

Description: SystemVerilog 写的APB总线接口的uart 代码，带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)
Platform: | Size: 16384 | Author: 容止 | Hits:

[VHDL-FPGA-Verilog] Uart-Verilog

Description: verilog实现串口通讯，包括verilog代码和testbench代码(verilog serial communication, including the verilog code and testbench Code)
Platform: | Size: 791552 | Author: 代工 | Hits:

[VHDL-FPGA-Verilog] uart_rx

Description: Verilog实现的RS232发送和接收程序，有完成的verilog代码，testbench等。(UART send and receive verilog code, including verilog source code, testbench etc.)
Platform: | Size: 452608 | Author: 66778899 | Hits:
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