Description: verilog描述
23：59：59-00：00：00自减计时器
按set键，进入设置，依次是反向计时，小时，分钟，秒设置，然后有进入反向计时，
在方向计时状态，按timmer键，进入计时，在计时状态，按timmer可以暂停和计时切换，
暂停状态，按ADJ,直接清零，设置状态按timmer键或是60秒无外部输入信号，退出设置状态-Verilog description 23:59:59-00:00:00 since by timer set by the key, enter the settings, followed by reverse-time, hours, minutes, seconds set, and then have access to reverse time, in the direction of time, and by Timmer key, enter the time, in time, and may be suspended by Timmer and the time switch, paused, press ADJ, directly cleared, set state by Timmer key or 60 seconds without external input signal from the set state Platform: |
Size: 2048 |
Author:申刚 |
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Description: 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model Platform: |
Size: 1024 |
Author:劉季泓 |
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Description: 用C#写的跑表，用于学习Timer控件和C#下的stopwatch类，在VS.net 2005下运行通过.-Using C# to write the stopwatch for the study and Timer controls and C# under the stopwatch class, VS.net 2005 in the run through. Platform: |
Size: 38912 |
Author:weixin |
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Description: 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。
使用计时器的方式产生时钟波形。
提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other modules. The use of the timer-generated clock waveform. To provide for the FPGA clock even sub-frequency, odd-numbered sub-frequency, pulse width is always functions. Platform: |
Size: 1466368 |
Author:icemoon1987 |
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Description: 本代码用verilog语言描述，在nios上操作，实现了定时器的设置和中断操作，并结合timestamp读取程序运行的时间。-The code to use verilog language to describe, in nios on operation, to achieve the timer settings and interrupt operation, combined with the timestamp reads the program run. Platform: |
Size: 19273728 |
Author:普尔 |
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Description: verilog实现数字式秒表，秒表有一个按键开关：当电路处于“初始”状态时，第一次按键，计时开始（“计时”状态）；再
次按键。计时停止（“停止”状态）；第三次按键，计时器复位为 0’0’.0’’，且电路恢复到“初始”状态。详见压缩文件包内pdf说明。-Verilog in implementing digital stopwatch, stopwatches have a key switch: when the circuit is in the initial State, first press the set start time ( time )
Time button. Timer stop ( stop ) the third button, the timer is reset to 0 0 .0 and restore circuits to initial State. See note compressed packages PDF. Platform: |
Size: 10483712 |
Author:崔超 |
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Description: SDRAM verilog 代码，已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits.
1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode
2. the read agent is active enough to refresh the RAM (if not, add a refresh timer) Platform: |
Size: 2048 |
Author:bryan |
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Description: 利用verilog设计的停车场中的计数器计时器和计费器，完成智能管理效果-Use the counter timer and meter parking lot in the Verilog design, intelligent management Platform: |
Size: 5120 |
Author:陆晓忆 |
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Description: 设计一个用于篮球比赛的定时器。要求：
（1）定时时间为24秒，按递减方式计时，每隔1秒，定时器减1；
（2）定时器的时间用两位数码管显示；
（3）设置两个外部控制开关，开关K1控制定时器的直接复位/启动计时，开关K2控制定时器的暂停/连续计时；当定时器递减计时到零（即定时时间到）时，定时器保持零不变，同时发出报警信号，报警信号用一个发光二极管指示。
（4）输入时钟脉冲的频率为50MHz。
（5）用Verilog HDL语言设计，用Modelsim软件做功能仿真，用Quartus II综合。(Design a basketball game timer. Requirements:
(1) the timing time is 24 seconds, which is timed in a decreasing manner. Every second, the timer is reduced by 1.
(2) the time of the timer is displayed with two digital tubes;
(3) two external control switches are set. Switch K1 controls the direct reset/start time of the timer, and switch K2 controls the pause/continuous time of the timer. When the timer declinates to zero (that is, when the timer time reaches zero), the timer remains unchanged, and an alarm signal is sent at the same time. The alarm signal is indicated by a light-emitting diode.
(4) the input clock pulse frequency is 50MHz.
(5) design with Verilog HDL language, perform function simulation with Modelsim software, and integrate with Quartus II.) Platform: |
Size: 1972224 |
Author:严老板 |
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