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[Other resource] Carrier & Symbol Timing Recovery

Description: Carrier & Symbol Timing Recovery-Carrier Symbol Timing Recovery
Platform: | Size: 27418 | Author: 叶盛 | Hits:

[File Operate] Timing

Description: Timing execution time can write their own,Let us study it slowly huh
Platform: | Size: 543 | Author: 马强 | Hits:

[Develop Tools] VESA-Monitor-Timing-Standard

Description: VESA monitor timing standard
Platform: | Size: 455187 | Author: archerkite | Hits:

[VHDL-FPGA-Verilog] VGA Output

Description: VGA Timing Output display
Platform: | Size: 4763 | Author: sisi12343@sina.com | Hits:

[Data structs] graph, heap, sorting, timing source code-- common datastruct

Description: graph, heap, sorting, timing source code
Platform: | Size: 109937 | Author: china_rmb@sohu.com | Hits:

[SourceCode] graph, heap, sorting, timing source code-- common datastruct

Description: graph, heap, sorting, timing source code
Platform: | Size: 109937 | Author: china_rmb@sohu.com | Hits:

[matlab] Carrier & Symbol Timing Recovery

Description: Carrier & Symbol Timing Recovery-Carrier Symbol Timing Recovery
Platform: | Size: 26624 | Author: 叶盛 | Hits:

[Embeded-SCM Develop] Timing

Description: <系统时序基础理论.doc>,9页 虽然简短,但从其文其图及其公式可以看出,是CPLD/FPGA设计的必修课. -<System timing based on the theory. Doc>, 9 page, though brief, but its text, its map and its formula can be seen is the CPLD/FPGA design courses.
Platform: | Size: 223232 | Author: pc_repair | Hits:

[matlab] timing

Description: 采用GARDNER算法的定时模块的仿真，输入每个符号4个采样点，通过内插，输出一个样本值-GARDNER algorithm used the timing of the simulation module, enter each symbol four sampling points, by interpolation, the output value of one sample
Platform: | Size: 1024 | Author: wwyy | Hits:

[Books] VESA-Monitor-Timing-Standard

Description: VESA monitor timing standard
Platform: | Size: 454656 | Author: archerkite | Hits:

[ERP-EIP-OA-Portal] Interpreting-the-Timing-Diagram

Description: 国外经典教材-如何读懂时序图 是理解时序图的入门教材-Classic teaching abroad- How to read timing diagram
Platform: | Size: 655360 | Author: 黄富德 | Hits:

[Documents] 6732448-Basic-Timing-Constraints-Tutorial

Description: timing constraints in fpga
Platform: | Size: 124928 | Author: kata | Hits:

[Industry research] Timing

Description: 定时误差估计，精度很高，算法简单易于实现，很值得参考！-Timing error estimates, precision is high, the algorithm simple and easy to implement, it is worth considering!
Platform: | Size: 3445760 | Author: 王哥 | Hits:

[Other] 2004-Timing

Description: Timing 数字集成电路中时序分析和优化技术 作者Sachin Sapatnekar -Timing Sachin Sapatnekar
Platform: | Size: 5482496 | Author: 王芯 | Hits:

[Documents] timing

Description: timing recovery using squaring method
Platform: | Size: 462848 | Author: danish | Hits:

[matlab] timing

Description: sc-fde（单载波频域均衡）系统的定时功能仿真-sc-fde (single carrier frequency domain equalization) system timing functional simulation
Platform: | Size: 1024 | Author: cy | Hits:

[Special Effects] VGA-timing

Description: VGA 图像时序分析，是VGA测试的入门资料-VGA timing, very good for study VGA
Platform: | Size: 1145856 | Author: hahabird1972 | Hits:

[Software Engineering] How-to-read-timing-diagram

Description: 时序 ，就是按照一定的时间顺序给出信号 就能得到你想要的数据，或者把你要写的数据写进芯片 -Timing Timing is given by a certain time sequence signal can get the data you want, or you write the data written into the chip
Platform: | Size: 101376 | Author: 李文 | Hits:

[SCM] can-bus-bit-timing-setting

Description: 在CAN总线中,位定时有一点小错误就会导致总线性能严重下降。虽然在许多情况下，位同步会修补由于位定时设置不当而产生的错误，但不能完全避免出错情况，并且在遇到两个或多个CAN节点同时发送的情况时，错误的采样点会使节点启动错误认可标志，使节点不能赢得总线上的任何活动。因此要分析、解决这样的错误就需要对CAN总线位定时中的位同步和CAN节点的工作过程有一个深入的了解。本文描述了CAN总线位同步的运行规则以及如何对位定时的参数进行设置。-In the CAN bus, there is a little bit timing errors will lead to a serious decline in bus performance. Although in many cases, bit synchronization bit timer settings will fix improper because of errors, but can not completely avoid error conditions, and in the event of two or more CAN nodes simultaneously send the case, the error of the sampling points will node startup error recognition signs, so that nodes can not win any activity on the bus. Therefore, to analyze and solve this error you need for the CAN bus bit timing and bit synchronization in CAN nodes have a working understanding of the process. This paper describes the operation of the CAN bus bit synchronization bit timing rules and how to set the parameters.
Platform: | Size: 28672 | Author: 陈晓楠 | Hits:

[Other] VESA Timing标准

Description: 查看标准vesa timing规范，便于显示器产品开发(View the standard VESA timing specification)
Platform: | Size: 613376 | Author: ztl333 | Hits:
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