Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - timing analysis

Search list

[Other] statictiminganalysis

Description: 静态时序分析，是IC design后端设计中最基本的基础部分-static timing analysis, design of the IC backend design the most basic part
Platform: | Size: 673792 | Author: stefshen | Hits:

[Documents] ise

Description: xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能-Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance
Platform: | Size: 271360 | Author: 江巧微 | Hits:

[VHDL-FPGA-Verilog] constraint_design_and_timing_analysis

Description: 关于Xilinx_ISE环境下，约束设计和时序分析的应用指南，蛮实用的-On Xilinx_ISE circumstances, bound by the design and timing analysis application guide, very practical
Platform: | Size: 975872 | Author: joan | Hits:

[Software Engineering] DDR

Description: 关于DDR SDRAM的详细原理和时序分析,对于开发设计有很大使用价值-DDR SDRAM on detailed principles and timing analysis, design for the development of a great value
Platform: | Size: 2201600 | Author: 王平 | Hits:

[Documents] Static_Timing_Analysis

Description: 静态时序分析设计的经典教程书籍 全面，权威的讲解，丰富的内容举例-Static timing analysis tutorial books classic design a comprehensive, authoritative presentation, rich content, for example
Platform: | Size: 673792 | Author: zhangxudong | Hits:

[Static control] StaticTimingAnalysis

Description: 静态时序分析（Static Timing Analysis简称STA）经由完整的分析方式判断IC是否能够在使用者的时序环境下正常工作，对确保IC质量之课题，提供一个不错的解决方案。然而，对于许多IC设计者而言，STA是个既熟悉却又陌生的名词。本文将力求以简单叙述及图例说明的方式，对STA的基础概念及其在IC设计流程中的应用做详尽的介绍。-Static timing analysis (Static Timing Analysis referred to as STA) through a complete analysis of ways to determine whether IC timing in the user' s normal work environment, to ensure the quality of the subject IC to provide a good solution. However, for many IC design engineers, STA is both familiar yet strange term. This paper will seek to a simple narrative, and legend in the manner described, the basic concept of the STA and its application in IC design process of doing a detailed introduction.
Platform: | Size: 726016 | Author: 王铭义 | Hits:

[Embeded-SCM Develop] static_time_analysis

Description: Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.
Platform: | Size: 7168 | Author: ankit | Hits:

[Industry research] PrimeTime_Advanced_Timing_Analysis_User_Guide

Description: PrimeTime Advanced Timing Analysis User Guide
Platform: | Size: 1958912 | Author: kerwin fu | Hits:

[VHDL-FPGA-Verilog] modelsim-timing-analysis

Description: 自己整理的一个关于如何使用modelsim进行功能仿真，时序仿真和布局布线的后仿真的文档，例子是抄的，针对的版本是modelsim se6.2b-Their finishing a feature on how to use modelsim for simulation, timing simulation and post-layout simulation of the document, copy the example is for the version of modelsim se6.2b
Platform: | Size: 705536 | Author: 雍振强 | Hits:

[Other] Altera-timing-analysis

Description: altera的静态时序分析基本原理和时序分析模型-altera basic principles of static timing analysis and timing analysis model
Platform: | Size: 334848 | Author: kizoe | Hits:

[VHDL-FPGA-Verilog] analysis

Description: 很经典的华为时序分析资料，用于电路的时序分析-Huawei is the classic time series analysis data for circuit timing analysis
Platform: | Size: 699392 | Author: hemiao | Hits:

[Windows Develop] Maxplus-timing-simulation

Description: 主要介绍Max_plus_的时序仿真与时序分析，对刚入门的很有帮助意义。-Introduced Max_plus_ timing simulation and timing analysis, meaning just getting started helpful.
Platform: | Size: 1224704 | Author: Aaran | Hits:

[VHDL-FPGA-Verilog] Timing-analysis

Description: FPGA玩转Altera之时序篇，包括时序分析注意事项-Altera play the FPGA XuPian, including timing analysis the matters needing attention
Platform: | Size: 16743424 | Author: 蔡历鑫 | Hits:

[Other] Timing-Analysis-Overview

Description: FPGA的时序分析利器，入门不错，适合初学者-Timing Analysis Overview
Platform: | Size: 236544 | Author: 瑾琨 | Hits:

[VHDL-FPGA-Verilog] Timing-Analysis

Description: 关于VHDL/VERILOG进行EDA设计时序分析时需要注意的一些需要注意的问题及处理策略，保证相当实用，请需要的人参考-VHDL/VERILOG the EDA design timing analysis need to pay attention to some issues that need attention and treatment strategies, guaranteed to be quite practical, please need Reference
Platform: | Size: 10624000 | Author: 张炽 | Hits:

[VHDL-FPGA-Verilog] Timing

Description: 国外关于时序设计的一本非常好的书，写得非常详细，包括时序的分析的原理-Abroad on timing design of a very good book, written in great detail, including the principle of timing analysis, etc.
Platform: | Size: 5533696 | Author: linhanxiong | Hits:

[Successful incentive] timing

Description: FPGA设计时序约束及时序分析资料。详细介绍了时序约束中的基本概念、常用约束、如何分析时序等。-FPGA design timing constraints and timing analysis. Details of the timing constraints of the basic concepts, common constraints, such as how to analyze timing.
Platform: | Size: 2521088 | Author: kan | Hits:

[VHDL-FPGA-Verilog] IO-timing-constrain-in-fpga

Description: 对FPGA的IO口的时序分析小结，能够详细理解其约束时序规则-FPGA timing analysis summary of IO port, capable of a detailed understanding of its timing constraint rules
Platform: | Size: 189440 | Author: 张龙 | Hits:

[Software Engineering] altera-timing

Description: Altera时序分析基础，帮助提升时序分析能力，建立时序分析模型。-The base of Altera timing analysis.
Platform: | Size: 531456 | Author: 王欢 | Hits:

[Documents] Static Timing Analysis

Description: 静态时序分析，有很详细的例子和图标说明，对于FPGA工程师非常有用，对于IC工程师也非常有用！(Static timing analysis, there are very detailed examples and icon descriptions.)
Platform: | Size: 4658176 | Author: 姚小菜123 | Hits:
« 12 3 4 5 6 7 8 9 10 »

CodeBus www.codebus.net