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[
VHDL-FPGA-Verilog
]
delay_line
Description:
延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module
Platform:
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Size:
1024
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Author:
zhangjing
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Search - tunable delay line VERIL
Search - tunable delay line VERIL