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[
VHDL-FPGA-Verilog
]
twice_freqencey
Description:
用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真-Verilog multiplier used directly to complete the algorithm, as a result of timing simulation quartus8.0
Platform:
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Size:
231424
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Author:
nikui
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