Search - uart hdl

[Other resource] micro uart

Description: 硬件uart源程序verilog HDL，即相关文档-hardware UART Verilog HDL source, that the relevant documents
Platform: | Size: 342886 | Author: 陈正一 | Hits:

[Other resource] uart

Description: 实现简单的UART功能,在QUARTUS4.0下编译通过,采用VERILOG HDL编写.
Platform: | Size: 886 | Author: 不是 | Hits:

Description: 采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.
Platform: | Size: 431104 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] micro uart

Description: 硬件uart源程序verilog HDL，即相关文档-hardware UART Verilog HDL source, that the relevant documents
Platform: | Size: 343040 | Author: 陈正一 | Hits:

[Com Port] verilog_UART

Description: UART verilog hdl 实现-UART Verilog HDL achieve
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] Altera_uart_Verilog

Description: FPGA/CPLD应用,uart的Verilog HDL原码-FPGA/CPLD applications, UART Verilog HDL source
Platform: | Size: 10240 | Author: cyberworm | Hits:

[Other] uartvhrilog

Description: This Verilog HDL description implements a UART.
Platform: | Size: 3072 | Author: chenhe | Hits:

[Com Port] uart16550

Description: uart16550　ＩＰ核ＨＤＬ源代码，对设计自己uart的人员和学习串口通讯有一定的参考价值！其中，附有详细的所明文档！-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
Platform: | Size: 291840 | Author: Jack | Hits:

[VHDL-FPGA-Verilog] uartverlog

Description: 占用资源少的verilog HDL uart接口；采用固定波特率115200，可以修改程序中的分频来修改波特率，模式为1个启始位，8位数据位，1个停止位；带1字节缓存；当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Platform: | Size: 2048 | Author: 张诚 | Hits:

[Other Embeded program] uart

Description: 实现简单的UART功能,在QUARTUS4.0下编译通过,采用VERILOG HDL编写.-Simple UART functions in the compiler under QUARTUS4.0 through using VERILOG HDL preparation.
Platform: | Size: 1024 | Author: 不是 | Hits:

[Com Port] uart2iic

Description: UART转I2C的Verilog HDL代码，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写-UART to I2C of the Verilog HDL code, by the Beijing University of Posts and Telecommunications VerilogHDL design and EDA technology infrastructure Teacher preparation
Platform: | Size: 3072 | Author: emulous | Hits:

[VHDL-FPGA-Verilog] eeprom

Description: eeprom的Verilog HDL源代码，含eeprom的读写！Quartus II5.0平台测试通过！-EEPROM of the Verilog HDL source code, including reading and writing EEPROM! Quartus II5.0 platform test!
Platform: | Size: 521216 | Author: | Hits:

[Com Port] rec

Description: uart串口通信程序用VERILOG HDL　编写　可以有效应用于FPGA上-UART serial communication program with VERILOG HDL can be effectively used in the preparation of the FPGA
Platform: | Size: 1024 | Author: 德刚 | Hits:

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[Other resource] micro uart

[Other resource] uart

[Com Port] uartok

[VHDL-FPGA-Verilog] micro uart

[Com Port] verilog_UART

[VHDL-FPGA-Verilog] Altera_uart_Verilog

[Other] uartvhrilog

[Com Port] uart16550

[VHDL-FPGA-Verilog] uartverlog

[Other Embeded program] uart

[Com Port] uart2iic

[VHDL-FPGA-Verilog] eeprom

[Com Port] rec

[VHDL-FPGA-Verilog] Fusion_UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart_txd

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

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