Search - uart testbench

[VHDL-FPGA-Verilog] H16550_2[1].0V

Description: 专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550 ，包含完整的使用说明手册、testbench、可综合，如果被网站认可，将继续上传其余的几个更好的core。-specialized processor and peripheral interfaces famous ipcore CAST product manufacturers UART H16 550, including full use manual testbench can be integrated, if the site is approved, the rest will continue to upload a few better core.
Platform: | Size: 386048 | Author: 宋云成 | Hits:

[Com Port] UART

Description: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

[VHDL-FPGA-Verilog] UARTtransmitter

Description: UART Transmitter. VHDL code and its testbench.
Platform: | Size: 2048 | Author: mehmet | Hits:

[VHDL-FPGA-Verilog] uart-vhdl-testbench

Description: simple uart vhdl behavioural model (package) vhdl testbench example
Platform: | Size: 2048 | Author: Mark | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
Platform: | Size: 25600 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] uart2bus_latest.tar

Description: 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
Platform: | Size: 224256 | Author: robin | Hits:

[VHDL-FPGA-Verilog] UART

Description: UART发送verilog源码，波特率115200，以及testbench源码-Send verilog source UART baud rate 115200, and testbench source
Platform: | Size: 67584 | Author: 宁馫圈 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 这是一个uart串口实现16550的实现，代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
Platform: | Size: 35840 | Author: wangli | Hits:

[Other Embeded program] uart_tb

Description: Uart testbench in SV
Platform: | Size: 1024 | Author: Sweetu | Hits:

[MPI] uart

Description: verilog实现UART收发源码内有testbench-the UART transceiver Source for verilog implementation With testbench
Platform: | Size: 3072 | Author: 王军 | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart veilog源码含有testbench-uart verilog
Platform: | Size: 2048 | Author: 王维 | Hits:

[VHDL-FPGA-Verilog] uart_tb

Description: simple UART testbench code.inlucding
Platform: | Size: 1024 | Author: jason | Hits:

[Embeded-SCM Develop] uart_tb

Description: Uart testbench in SV
Platform: | Size: 1024 | Author: 闯黄扣分 | Hits:

[VHDL-FPGA-Verilog] RS422_UART

Description: RS422 串口通讯（包括 testbench，虚拟RAM，数据收发，波特率生成，数据接收抗干扰）-RS422 UART testbench BaudGen
Platform: | Size: 7168 | Author: 李俊 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 这是一个串口通讯模块，从串口接收14个数据后用于计算并将计算结果从串口发送出去，里面包含testbench。-This is a serial communication module 14 the serial port to receive data used to calculate the results and sent the serial port, which contains the testbench.
Platform: | Size: 7735296 | Author: 阿力 | Hits:

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[VHDL-FPGA-Verilog] H16550_2[1].0V

[Com Port] UART

[VHDL-FPGA-Verilog] UARTtransmitter

[VHDL-FPGA-Verilog] uart-vhdl-testbench

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart2bus_latest.tar

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] verilog

[Other Embeded program] uart_tb

[MPI] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart_tb

[Embeded-SCM Develop] uart_tb

[VHDL-FPGA-Verilog] RS422_UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART-master

[VHDL-FPGA-Verilog] apb_uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] Uart-Verilog

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