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Description: The UART (Universal Asynchronous Receiver/Transmitter) core provides serial
communication capabilities, which allow communication with modem or other external
devices, like another computer using a serial cable and RS232 protocol. This core is
designed to be maximally compatible with the industry standard National
Semiconductors’ 16550A device.
-The UART (Universal Asynchronous Receive r / Transmitter) core provides serial Communic ation capabilities, which allow communication with the modem or other e xternal devices, like another computer using a serial cable and R RS232 protocol. This core is designed to be maxim ally compatible with the industry standard Nat ional Semiconductors' 16550A device.
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Size: 187095 |
Author: 邓云 |
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Description: uart16550 ＩＰ核
ＨＤＬ源代码，对设计自己uart的人员和学习串口通讯有一定的参考价值！其中，附有详细的所明文档！-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
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Size: 291778 |
Author: Jack |
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Description: 串uart的vhdl，verilog，lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)\\uart 源码 (Verilog)\\uart 源码 (VHDL)\\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \\ uart source (Verilog) \\ uart source (VHDL) \\ uart16550.tar
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Size: 295101 |
Author: efly |
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Description: uart source code from opencore
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Size: 202890 |
Author: liuKe |
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Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。
Platform: |
Size: 10619 |
Author: David.Mr.Liu |
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Description: UART16550 controller, verilog
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Size: 245356 |
Author: YangYG |
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Description: uart16550 ip core 通用异步收发器vhdl源代码
Platform: |
Size: 247062 |
Author: 姓名 |
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Description: The UART (Universal Asynchronous Receiver/Transmitter) core provides serial
communication capabilities, which allow communication with modem or other external
devices, like another computer using a serial cable and RS232 protocol. This core is
designed to be maximally compatible with the industry standard National
Semiconductors’ 16550A device.
-The UART (Universal Asynchronous Receive r/Transmitter) core provides serial Communic ation capabilities, which allow communication with the modem or other e xternal devices, like another computer using a serial cable and R RS232 protocol. This core is designed to be maxim ally compatible with the industry standard Nat ional Semiconductors' 16550A device.
Platform: |
Size: 187392 |
Author: 邓云 |
Hits:
Description: uart16550 ＩＰ核
ＨＤＬ源代码，对设计自己uart的人员和学习串口通讯有一定的参考价值！其中，附有详细的所明文档！-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
Platform: |
Size: 291840 |
Author: Jack |
Hits:
Description: 串uart的vhdl，verilog，lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Platform: |
Size: 294912 |
Author: efly |
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Description: uart source code from opencore
Platform: |
Size: 202752 |
Author: liuKe |
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Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
Platform: |
Size: 10240 |
Author: David.Mr.Liu |
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Description: UART16550 controller, verilog
Platform: |
Size: 245760 |
Author: YangYG |
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Description: uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code
Platform: |
Size: 246784 |
Author: 姓名 |
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Description: openrisc mini_or1200, 包括 or1200、uart16550、dbg_interface、mem_if(片上内存)这几部分。-openrisc mini_or1200, including or1200, uart16550, dbg_interface, mem_if (memory chip) in these parts.
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Size: 841728 |
Author: billfeng |
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Description: Ｕａｒｔ 串口的verilog实现已调试通过-verilog
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Size: 39936 |
Author: wangli |
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Description: opcore.org "uart16550" 项目的testbench-test bench of "uart16550" project
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Size: 7168 |
Author: machenghai |
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Description: uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code.
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Size: 1760256 |
Author: CloudZhang |
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Description: UART控制器，集成FIFO，寄存器，数据位宽8位-UART controller, with FIFO, register, databus 8bits
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Size: 8192 |
Author: huangluyang |
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Description: UART16550 的开发核的详细说明文档-UART16550 detailed description of the development of nuclear documents
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Size: 144384 |
Author: 东东 |
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