Location:
Search - ufm
Search list
Description: Altera epm240 的ufm调用。
Platform: |
Size: 226404 |
Author: Potossas |
Hits:
Description:
Platform: |
Size: 233094 |
Author: sqazsq |
Hits:
Description: HK110DM ,HK588TP,HKP800T,HK-P600T打印机C语言例程以及相关的动态链接库-HK110DM, HK588TP, HKP800T. HK-P600T printers C language routines and the related dynamic link library
Platform: |
Size: 3357696 |
Author: axxxxx |
Hits:
Description: Altera epm240 的ufm调用。-Altera epm240 the UFM call.
Platform: |
Size: 226304 |
Author: Potossas |
Hits:
Description: 完整的ALTERA MAXⅡEPM570试验板资料，包括原理图和PCB图，BOM表，可以直接做板。-Complete ALTERA MAX Ⅱ EPM570 test boards, including schematic and PCB diagram, BOM tables, plates can be directly done.
Platform: |
Size: 433152 |
Author: blur |
Hits:
Description: ALTERA公司的MAXⅡ系列CPLD的内部flash使用教程，内容很详细，图文并茂，英文版。-ALTERA s MAX Ⅱ series CPLD to use the internal flash tutorial is very detailed, with illustrations in English.
Platform: |
Size: 848896 |
Author: blur |
Hits:
Description: BJ-EPM240V2实验例程以及说明文档实验之十四MAX II的UFM模块使用实例-BJ-EPM240V2 experimental test routines as well as documentation of the MAX II 14 UFM module uses examples
Platform: |
Size: 740352 |
Author: 王建毅 |
Hits:
Description: Unfied Modelling searching using Fuzzy logic
Platform: |
Size: 98304 |
Author: vvishalbauskar |
Hits:
Description: 了解maxii的内部结构，学会调用里面的ufm，充分利用其资源-Understand the internal structure of maxii learn to call the inside ufm, make full use of its resources
Platform: |
Size: 564224 |
Author: chalk |
Hits:
Description: 了解max ufm的内部结构和工作原理，学习VHDL的编程方法-Learn max ufm internal structure and working principle of learning VHDL programming method
Platform: |
Size: 418816 |
Author: chalk |
Hits:
Description: CLUE - A Clue And UFM Based Searching for the image file
Platform: |
Size: 456704 |
Author: vvishal |
Hits:
Description: The MAX II CPLD has the following features:
■ Low-cost, low-power CPLD
■ Instant-on, non-volatile architecture
■ Standby current as low as 29 μA
■ Provides fast propagation delay and clock-to-output times
■ Provides four global clocks with two clocks available per logic array block (LAB)
■ UFM block up to 8 Kbits for non-volatile storage
■ MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V
or 1.8 V
■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels-The MAX® II family of instant-on, non-volatile CPLDs is based on a 0.18-μm, 6-layermetal-
flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210
equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices offer high
I/O counts, fast performance, and reliable fitting versus other CPLD architectures.
Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system
programmability (ISP), MAX II devices are designed to reduce cost and power while
providing programmable solutions for applications such as bus bridging, I/O
expansion, power-on reset (POR) and sequencing control, and device configuration
control.
Platform: |
Size: 612352 |
Author: 王广龙 |
Hits:
Description: 基于fpga的verilog写的MAX2的ufm模块使用实例-Module uses examples based on the fpga' s verilog wrote the MAX2 the ufm
Platform: |
Size: 95232 |
Author: yeguowu |
Hits:
Description: UFM with I2C MAX II CPLD Design Example
Platform: |
Size: 114688 |
Author: jan |
Hits:
Description: MAX® II devices have an internal oscillator as part of the user flash
memory (UFM). The internal oscillator can be used to meet the clocking
requirements of many designs and eliminate the requirement for an
external clock circuitry. This application note describes the instantiation
of the internal oscillator and its usage.-MAX® II devices have an internal oscillator as part of the user flash
memory (UFM). The internal oscillator can be used to meet the clocking
requirements of many designs and eliminate the requirement for an
external clock circuitry. This application note describes the instantiation
of the internal oscillator and its usage.
Platform: |
Size: 218112 |
Author: kiam |
Hits: