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[Other resource] urisic

Description: 用代码来控制urisc控制器，实现微码控制单元
Platform: | Size: 2880 | Author: 熊良鹏 | Hits:

[Other resource] urisc

Description: URISC 处理器由数据单元和控制单元组成。数据单元中包含保存运算数据和运算结果的数据寄存器，也包括用来完成数据运算的组合逻辑电路单元。控制单元用来产生控制信号序列，以决定何时进行何种数据运算。控制单元要从数据单元得到条件信号，以决定继续进行那些数据运算，数据单元要产生输出信号，数据运算状态等有用信息。
Platform: | Size: 2034 | Author: 良芯 | Hits:

[Program doc] urisc报告

Description: 1. 学习复杂数字系统的设计，调试和检测 2. 实现URISC系统的设计
Platform: | Size: 103424 | Author: wsyangcheng@gmail.com | Hits:

[VHDL-FPGA-Verilog] urisic

Description: 用代码来控制urisc控制器，实现微码控制单元-Use code to control urisc controllers, micro-code control unit realize
Platform: | Size: 3072 | Author: 熊良鹏 | Hits:

[VHDL-FPGA-Verilog] urisc

Description: URISC 处理器由数据单元和控制单元组成。数据单元中包含保存运算数据和运算结果的数据寄存器，也包括用来完成数据运算的组合逻辑电路单元。控制单元用来产生控制信号序列，以决定何时进行何种数据运算。控制单元要从数据单元得到条件信号，以决定继续进行那些数据运算，数据单元要产生输出信号，数据运算状态等有用信息。-URISC processor by the data unit and control unit. Data unit included in the preservation of data and computing the results of computing the data register, but also data used to complete a combination of computing logic circuit unit. Control unit used to generate the control signal sequence, to determine when and what data computing. Control unit from the data unit received condition signal to determine the continuation of the data computation, data unit to produce output signals, data, such as computing the state of useful information.
Platform: | Size: 2048 | Author: 良芯 | Hits:

[Other] URISC_PROCESSOR

Description: URISC处理器的VHDL实现,采用模块化思想自顶向下实现，内部自定义总线模块-URISC PROCESSOR
Platform: | Size: 423936 | Author: neo | Hits:

[VHDL-FPGA-Verilog] urisc

Description: 实现了精简指令集微处理器的数据路径和微代码控制单元两部分的功能-RISC microprocessor implemented data path and micro-code control unit features two
Platform: | Size: 2048 | Author: aimeelove | Hits:

[VHDL-FPGA-Verilog] URISC

Description: 一个完整的带I/O和RAM，ROM的URISC,可以完成A+B/2的运算。实际上，通过对ROM的手工编程，可以实现8为数据的加减乘除，已经更加复杂的运算。-An ultimate URISC With I/Os, a RAM, a ROM,which can complete A+ B/2 calculations. In fact, through the ROM of the manual programming, it can do more calculations,such as A+B,A-B,A*B,A/B,and so on.
Platform: | Size: 5120 | Author: 王斌 | Hits:

[VHDL-FPGA-Verilog] open8_urisc_latest.tar

Description: opencores urisc code
Platform: | Size: 74752 | Author: wangwei | Hits:

[Software Engineering] URISC

Description: URISC整个设计流程以及源代码、仿真结果-URISC throughout the design process as well as source code, simulation results
Platform: | Size: 293888 | Author: 韩晓敏 | Hits:

[VHDL-FPGA-Verilog] urisc_2011

Description: 这是一个urisc的作业，用于搭建一个单指令的处理器，-This is a urisc job, build a single instruction for the processor,
Platform: | Size: 3072 | Author: 张铖 | Hits:

[Other] urisc

Description: 自己用verilog编写的urisc程序，调试成功，压缩包里有仿真图像，值得学习参考。-Written in verilog urisc program debugging, simulation image compression bag, worth learning reference.
Platform: | Size: 312320 | Author: fengwei | Hits:

[Other] URISC

Description: 关于URISC的一组代码，包括各个模块的代码以及测试代码，还有报告说明书。内容非常详细。是清华大学微电子系研究生课程中数字集成系统设计的一个作业的PROJECT.-About URISC a set of code, including code and test code of each module, the reporting instructions. Very detailed. Department of Microelectronics, Tsinghua University post-graduate courses in digital integrated system design of a job Project.
Platform: | Size: 406528 | Author: 杨学硕 | Hits:

[VHDL-FPGA-Verilog] RISC

Description: URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)
Platform: | Size: 4096 | Author: Phystan | Hits:

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