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[Communicationlabview CRC16

Description: crc16的例子。用于modbus rtu方式通讯。使用labview编制,将下载文件后缀改为.vi-crc16 example. Kaubamaja for Modbus communication. Using LabVIEW establishment, download the file extension changed. Vi
Platform: | Size: 17408 | Author: 许艳 | Hits:

[VHDL-FPGA-VerilogCRC-Verilog

Description: 此是进行循环冗余效验的Verilog编码,适合多种标准,如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Platform: | Size: 3072 | Author: 藏瑞 | Hits:

[USB developusb_cvt_tool_0.1

Description: 该工具用于数字电路仿真中的usb数据文件转换: 1.可以把11比特的令牌包数据(crc5)或者任意字节的数据包数据(crc16)转换为可以作为仿真输入的dn dp文件。 2.可以根据仿真接收到的dn,dp数据,解析得到接收的真正11比特令牌包数据或者数据包数据。 3.此为0.1版本,后续的版本更新会让该工具更完善。-The tool for digital circuit simulation usb data file conversion: 1. Can be 11-bit token packet data (crc5) arbitrary bytes of data or packet data (crc16) conversion could serve as a simulation input file dn dp. 2. Can be received in accordance with simulation dn, dp data analysis to be receiving the real 11-bit token packet data or packet data. 3. This is the 0.1 version update will follow-up version of the tool even better.
Platform: | Size: 3943424 | Author: 肖子 | Hits:

[Software Engineeringusb_latest[1].tar

Description: sub opercore USB CRC5 and CRC16 Modules //// //// //// //// //// //// Author: Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// //// //// Downloaded from: http://www.opencores.org/cores/usb/-sub opercore USB CRC5 and CRC16 Modules//////////////////////// Author: Rudolf Usselmann//////// rudi@asics.ws//////////////////////// Downloaded from: http://www.opencores.org/cores/usb/
Platform: | Size: 196608 | Author: hajc | Hits:

[LabViewCRC-pudn

Description: CRC16的9个LabVIEW算法CCITT,CCITT-KERMIT,CCITT-X25,CCITT-XMODEM,DNP,IBM,MAXIM,MODBUS,USB,开发环境LabVIEW2013-9 LabVIEW algorithm of CRC16: CCITT,CCITT-KERMIT,CCITT-X25,CCITT-XMODEM,DNP,IBM,MAXIM,MODBUS,USB The development environment version is LabVIEW 2013
Platform: | Size: 113664 | Author: 刘昕 | Hits:

[USB developCRC5_CRC16_USB

Description: USB2.0数据包CRC 16,TOKEN令牌包是CRC5,VerilogHDL代码 多项式y=1+x^2+x^15+x^16; y=1+x^2+x^5; 只是串行1位的代码, 并行8位,16位没有上传(USB CRC 16 , VerilogHDL code polynomial(0_2_15_16); polynomial(0_2_5))
Platform: | Size: 6144 | Author: 诡迹xjn | Hits:

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