Search - usb in vhdl

[USB develop] usb

Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码
Platform: | Size: 1012462 | Author: 李华 | Hits:

[Software Engineering] USB_devide

Description: 利用最新的嵌入式开发工具EDK，在FPGA 中完成对PDIUSBD12 的硬件定制和固件编程，从而在FPGA 中实现U S B 控制器，并最终完成U S B 的枚举过程、驱动程序的开发和简单的应用。-Using the latest embedded development tools, EDK, in the FPGA completes its PDIUSBD12 custom hardware and firmware programming, in order to realize USB controller in the FPGA, and ultimately complete the USB enumeration process of driver development and simple应用.
Platform: | Size: 50176 | Author: pengrong | Hits:

[Software Engineering] usb2.0

Description: USB 通用串行总线技术规范简介,这个是中文的.找了好久啊!-USB Universal Serial Bus specification Introduction, is that this is in Chinese. Looking for a long time ah!
Platform: | Size: 40960 | Author: Liziler | Hits:

[VHDL-FPGA-Verilog] FT245_R_W

Description: USB芯片FT245BM读写代码,在Quartus II V7.2上测试成功!---Verilog语言.
Platform: | Size: 1644544 | Author: | Hits:

[USB develop] ISP1301[1]

Description: USB and OTG ISP1301 Spec. Thank!
Platform: | Size: 183296 | Author: Teo Hsieh | Hits:

[MiddleWare] fpga_fifo_0122_02

Description: 可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序-To amend the agreement in the inside. Mainly cmos-fpga usb (68013a), except part of the procedure 68013a
Platform: | Size: 2322432 | Author: | Hits:

[Symbian] usb_dongle_fpga

Description: USB在FPGA上的实现，包括源码测试平台，测试向量，很实用。-USB realize in FPGA
Platform: | Size: 2037760 | Author: xiaojian | Hits:

[USB develop] usb

Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码-Test procedures for the use of 68,013, including 68,013 firmware (using the synchronous slave FIFO bulk read and write, EP2 OUT, EP6 IN), driver, PC-side test procedures. VHDL code of CPLD
Platform: | Size: 4731904 | Author: 李华 | Hits:

[VHDL-FPGA-Verilog] USB

Description: USB源代码，基于VHDL语言编写，在QuartusII上面已验证其功能-USB source code, based on the VHDL language, verified in QuartusII above its function
Platform: | Size: 5120 | Author: 周 | Hits:

[USB develop] USB

Description: USB 设计（包括一个参考设计，和标准U盘）-USB design (including a reference design, and standards for U disk)
Platform: | Size: 546816 | Author: zhangsan | Hits:

[VHDL-FPGA-Verilog] usb_phy.tar

Description: Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test bench available. This core is very simple and is proven in hardware. I see no point of writing a test bench at this time.
Platform: | Size: 7168 | Author: eldis | Hits:

[VHDL-FPGA-Verilog] Usb

Description: 基于FPGA的驱动设计，使得用户的USB驱动在此完美实现。-FPGA-based drive design makes the user' s USB drive in this work perfectly.
Platform: | Size: 770048 | Author: liuyu | Hits:

[Books] usb

Description: 在高速的数据采集或传输中，目前使用较多的都是采用USB 2．0接口控制器和FPGA或DSP实现的，本设计在USB 2．0接口芯片CY7C68013的Slave FIFO模式下，利用FPGA作为外部主控制器实现对FX2 USB内部的FIFO进行控制，以实现数据的高速传输。该模块可普遍适用于基于USB 2．0接口的高速数据传输或采集中。-In the high-speed data acquisition or transmission, the currently used are based on more USB 2.0 interface controller and the FPGA or DSP implementation, the design USB 2.0 interface chip CY7C68013 of the Slave FIFO mode, the use of FPGA as a the external FX2 USB host controller to realize the internal FIFO control, in order to achieve high-speed data transmission. The module can be generally applied based on high-speed USB 2.0 interface, transfer or acquisition of data.
Platform: | Size: 894976 | Author: jiang_jennifer | Hits:

[VHDL-FPGA-Verilog] WORKS

Description: Project of Adquisition Data, show in VGA and send to usb host
Platform: | Size: 9917440 | Author: lagartojj | Hits:

[VHDL-FPGA-Verilog] usb

Description: 程序说明: 本次实验控制开发板USB，与PC机进行通信，并在显示字符。目录说明: 工程在\project文件夹里面源文件和管脚分配在\rtl文件夹里面下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: In this experiment, control development board USB, and PC, to communicate, and display character. Catalog Description: The project \ project folder inside the source file and pins distributed in \ rtl folder inside download the file in the \ download folder inside,. Mcs for the PROM mode download files,. Bit for the JTAG debug download the file.
Platform: | Size: 80896 | Author: 军军 | Hits:

[VHDL-FPGA-Verilog] FT2232H_USB_Core

Description: 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieved. The core has internal FIFOs on the receive and transmit for improved throughput. For more information see FTDI s appnote "AN_130_FT2232H_Used_In_FT245 Synchronous FIFO Mode.pdf" Included: VHDL core, NIOS test application, PC test application
Platform: | Size: 6144 | Author: 李涛 | Hits:

[VHDL-FPGA-Verilog] Oscilloscope

Description: The design is designed partly in VHDL, partly in schematic drawings and targets a Xilinx Spartan-2E FPGA. However, since the design was tailored specifically for the aforementioned boards it is highly unlikely that it can be ported to other hardware. The circuits were designed on a Windows XP using the Xilinx WebPack 6.2 tool. The transfer of the design to the FPGA was carried out either with the Xilinx Impact tool through a parallel JTAG cable or with the Digilent Export utility through a USB JTAG cable.
Platform: | Size: 1854464 | Author: sami | Hits:

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[USB develop] usb

[Software Engineering] USB_devide

[Software Engineering] usb2.0

[VHDL-FPGA-Verilog] FT245_R_W

[USB develop] ISP1301[1]

[MiddleWare] fpga_fifo_0122_02

[Symbian] usb_dongle_fpga

[USB develop] usb

[VHDL-FPGA-Verilog] USB

[USB develop] USB

[VHDL-FPGA-Verilog] usb_phy.tar

[VHDL-FPGA-Verilog] Usb

[Books] usb

[VHDL-FPGA-Verilog] WORKS

[VHDL-FPGA-Verilog] usb

[VHDL-FPGA-Verilog] FT2232H_USB_Core

[VHDL-FPGA-Verilog] Oscilloscope

[VHDL-FPGA-Verilog] usb

[VHDL-FPGA-Verilog] fpga-usb

[USB develop] USB-1.1-IP-CORE-VHDL

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