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Description: USBHostSlave is a USB 1.1 host and Device IP core.
– Supports full speed (12Mbps) and low speed (1.5Mbps) operation.
– USB Device has four endpoints, each with their own independent FIFO.
– Supports the four types of USB data transfer control, bulk, interrupt, and isochronous
transfers.
– Host can automatically generate SOF packets.
– 8-bit Wishbone slave bus interface.
– FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core.
– Supports full speed (12Mbps) and low speed (1.5Mbps) operation.
– USB Device has four endpoints, each with their own independent FIFO.
– Supports the four types of USB data transfer control, bulk, interrupt, and isochronous
transfers.
– Host can automatically generate SOF packets.
– 8-bit Wishbone slave bus interface.
– FIFO depth configurable via paramters.
Platform: |
Size: 6144 |
Author: polito |
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Description: USB 1.1 slave/device IP core. Default configuration is 6 endpoints:
1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk
Out, 1 Interrupt IN. Includes control engine, providing full enumeration
process in hardware - no external micro-controller necessary.
Derived from my USB 2.0 Function IP core, except all the high speed
support logic has been ripped out and the interface was changed from
shared memory to FIFO based.
A basic test bench is now included as well. It should be viewed
as a starting point to write a more comprehensive and complete
test bench.
I expect the users of this core to have some fundamental USB knowledge
and be familiar with the UTMI specification and with the general USB
transceivers (e.g. from philips). If you are not familiar with these two
you should check out www.usb.org and read up on this subject ...
Platform: |
Size: 59392 |
Author: Andrey |
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Description: Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(Multi-MASTER):仲裁算法用于定义 支持各种各样的IP核互联，包括USB、双向总线、复用器互联等 同步逻辑设计 非常简单的时序标准 与硬件实现技术无关(FPGA, ASIC等) 与设计工具无关。
相对于其他的IP核接口规范来说，Wishbone接口规范具有简单、开放、高效、利于实现等特点而且完全免费，并没有专利保护。基于上述优点，因此采用Wishbone总线进行接口设计。本文对Wishbone总线接口的设计参考了OpenCore上的有关设计。-
Wishbone specification has the following characteristics : a simple , compact, and requires very little logic gates complete common data bus data transfer protocols, including single reader , fast transmission, read-modify- write cycle, the event cycle data bus width can be 8-64 bit support big-endian (big-endian) and the small end (litle-endian), the interface automatically convert between the two. Support memory mapping , FIFO memory , cross interconnection handshake protocol that allows rate control every clock cycle to achieve a data transfer support normal cycle ends , retry the end , wrong end of the bus cycle and other forms support for user-defined flags : The MASTER/SLAVE architecture supports multi- process (Multi-MASTER): arbitration algorithm is used to define support a variety of IP cores interconnected , including USB, bi-directional bus , multiplexer interconnection , etc. synchronous logic design very simple timing standards technology-indepe
Platform: |
Size: 12288 |
Author: 程浩武 |
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