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[Other resource] Triggersignalaccuratedataacquisitionsystemdesignde

Description: 在一些系统中，经常用到对触发信号延时一段时间后，再对某些目标信号进行采集，通常这段延时要求非常精确，还要做到范围可调，一般这种延时的最小时间单位小于100ns。如果选用普通微控制器，延时系统的操作界面比较容易实现，但是靠软件延时得到结果的准确性较低。考虑到芯片功能、开发环境以及接口方便等问题，最终选用一片常用的AlteraSVCPLD EPM7128SLC3411]作为系统的核心控制部分，来实现信号延时、输人设定、运行显示的功能。应用Veril- o苦2〕语言，在Altera的Quartus11WebEditio详3〕软件环境下进行编程仿真，最后烧写芯片进行系统硬件测试
Platform: | Size: 106842 | Author: hjh | Hits:

[Applications] crc8

Description: 8位CRC源代码-eight CRC source code
Platform: | Size: 2048 | Author: 李陵 | Hits:

[Applications] RISC Core_verilog

Description: RISC的指令VerilogHDL实现-RISC instructions to achieve VerilogHDL
Platform: | Size: 134144 | Author: 王晓东 | Hits:

[Windows Develop] ram

Description: verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
Platform: | Size: 1024 | Author: 杨艳 | Hits:

[Applications] crc_verilog

Description: 用于计算CRC的verilog HDL源码-CRC calculation for the Verilog HDL source
Platform: | Size: 10240 | Author: 刘波 | Hits:

[VHDL-FPGA-Verilog] alu

Description: verilog编写的alu模块-Verilog modules prepared by the ALU
Platform: | Size: 1024 | Author: 刘陆陆 | Hits:

[VHDL-FPGA-Verilog] fpga1394

Description: 这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.-This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.
Platform: | Size: 3072 | Author: 吴才路 | Hits:

[Other Embeded program] 发一个基于ModelSim仿真的Verilog源代码包

Description: 发一个基于ModelSim仿真的Verilog源代码包-made a ModelSim simulation based on the Verilog source code
Platform: | Size: 74752 | Author: 阿乐 | Hits:

[VHDL-FPGA-Verilog] FIR低通滤波器部分模块

Description: 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
Platform: | Size: 5120 | Author: 吴健宇 | Hits:

[VHDL-FPGA-Verilog] 16位乘法器

Description: 自已写的一个16X16的乘法器，速度比较慢。初学者练习练习！-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!
Platform: | Size: 2048 | Author: 唐勇翔 | Hits:

[VHDL-FPGA-Verilog] rtl

Description: 用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
Platform: | Size: 93184 | Author: 刘吉 | Hits:

[VHDL-FPGA-Verilog] 结合XILINXCPLD RS232通信(verilog)

Description: 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
Platform: | Size: 121856 | Author: 于飞 | Hits:

[VHDL-FPGA-Verilog] dianzizhong

Description: 这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!
Platform: | Size: 550912 | Author: 刘恒辉 | Hits:

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[Other resource] Triggersignalaccuratedataacquisitionsystemdesignde

[Applications] crc8

[Applications] RISC Core_verilog

[Windows Develop] ram

[Applications] crc_verilog

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] fpga1394

[Other Embeded program] 发一个基于ModelSim仿真的Verilog源代码包

[VHDL-FPGA-Verilog] FIR低通滤波器部分模块

[VHDL-FPGA-Verilog] 16位乘法器

[VHDL-FPGA-Verilog] rtl

[VHDL-FPGA-Verilog] 结合XILINXCPLD RS232通信(verilog)

[VHDL-FPGA-Verilog] dianzizhong

[VHDL-FPGA-Verilog] 8051verilog源码

[Other Embeded program] usbhostslave

[Crack Hack] MD5(verilog)

[VHDL-FPGA-Verilog] des-verilog

[VHDL-FPGA-Verilog] CRC校验参考设计_xilinx_verilog

[VHDL-FPGA-Verilog] 一些译码器源代码

[ARM-PowerPC-ColdFire-MIPS] embedded_risc

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