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[VHDL-FPGA-Verilog] riscmcu

Description: 精简CPU设计，需要的可以下来看看,是VERILOG语言写的-streamlined CPU design, the need to be down look at the language is written in verilog
Platform: | Size: 79872 | Author: 磊 | Hits:

[VHDL-FPGA-Verilog] 5_lined_cpu

Description: 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
Platform: | Size: 1024 | Author: 张健 | Hits:

[Windows Develop] CPU_verilog

Description: 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
Platform: | Size: 63488 | Author: xq | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器 在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Platform: | Size: 28672 | Author: Matgek | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
Platform: | Size: 187392 | Author: znl | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 实现了简单的CPU功能 采用三级流水线和超标量-CPU functions to achieve a simple three-stage pipeline and superscalar
Platform: | Size: 1735680 | Author: era | Hits:

[VHDL-FPGA-Verilog] pipelined-mips-cpu

Description: 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
Platform: | Size: 171008 | Author: jack chen | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
Platform: | Size: 2048 | Author: dylan | Hits:

[VHDL-FPGA-Verilog] 32bit-RISC-CPU-IP

Description: 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.
Platform: | Size: 33792 | Author: 张秋光 | Hits:

[VHDL-FPGA-Verilog] PipelineCPU2

Description: Modulsim下Verilog写的五级流水线32位简易CPU-five level pipeline CPU written in Verilog.
Platform: | Size: 772096 | Author: tiancai | Hits:

[VHDL-FPGA-Verilog] PIPELINE

Description: 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.
Platform: | Size: 8720384 | Author: zzh | Hits:

[VHDL-FPGA-Verilog] pipline

Description: 用verilog实现的流水线cpu,实现高效率的CPU基本运算-Pipeline cpu with verilog
Platform: | Size: 932864 | Author: 郭昕昳 | Hits:

[ARM-PowerPC-ColdFire-MIPS] PipelineCPU

Description: 这是我们设计的一个MIPS流水线CPU，基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于，5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型，这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句，从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU differences that each of the five pipeline stages maintenance a variable (SelType) indicates that the currently executing instruction types, this treatment data Adventure loaduse adventure or jump adventure when each segment can know The statement is being processed, in order to facilitate our processing.
Platform: | Size: 11357184 | Author: 武翔宇 | Hits:

[Other] proc_pipe

Description: A 5 stage pipeline CPU written in verilog codes
Platform: | Size: 35840 | Author: gnuhcyee | Hits:

[VHDL-FPGA-Verilog] cpu_design

Description: FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
Platform: | Size: 2428928 | Author: leo | Hits:

[Other] 0340196Lab3

Description: 这是用Verilog语言编写的带有pipeline功能的CPU，适合于学习计算机组织的同学-This is a Verilog language functions CPU with pipeline for students to learn computer organization
Platform: | Size: 484352 | Author: 王倩倩 | Hits:

[VHDL-FPGA-Verilog] mips

Description: Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
Platform: | Size: 15360 | Author: DY | Hits:

[VHDL-FPGA-Verilog] CPU_Verilog

Description: 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
Platform: | Size: 12288 | Author: fairchildfzc | Hits:

[VHDL-FPGA-Verilog] CPU-Pipeline

Description: 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
Platform: | Size: 14336 | Author: Si Cheng | Hits:
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