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[Other resource] D触发器的设计

Description: D触发器的设计 主要用在时序电路中。 所用语言为Verilog HDL.-D flip-flop with the main design of the timing circuit. The language used for Verilog HDL.
Platform: | Size: 3572 | Author: 李鹏 | Hits:

[Other resource] verilog

Description: verilog原理与应用 作者：Michael D. Ciletti
Platform: | Size: 398078 | Author: 严妙奇 | Hits:

[SourceCode] 带同步清0、同步置1 的D 触发器

Description: 带同步清0、同步置1 的D 触发器, Verilog HDL 源码
Platform: | Size: 172858 | Author: cccccs1988@126.com | Hits:

[Embeded-SCM Develop] Verilog DHL教程

Description: Verilog DHL教程-Verilog DHL course
Platform: | Size: 864256 | Author: zfhustb | Hits:

[VHDL-FPGA-Verilog] des-verilog

Description: des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
Platform: | Size: 67584 | Author: 杨云丰 | Hits:

[Embeded-SCM Develop] dff_UDP

Description: verilog实现，UDP描述带有异步复位的正边沿触发D触发器，test测试通过-verilog achieve, UDP asynchronous reset with a description of the fringe is triggered D flip-flop, test test pass
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] DCT

Description: 用verilog语言实现DCT编解码 附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Platform: | Size: 65536 | Author: 周韧研 | Hits:

[VHDL-FPGA-Verilog] djkrs

Description: d,jk,rs触发器的vhdl语言实现，简单明了-d, jk, rs flip-flop of the VHDL language, simple and clear
Platform: | Size: 70656 | Author: 周军 | Hits:

[SCM] Verilog

Description: DDS，FPGA产生，用verilog语言实现-DDS, FPGA generated using Verilog language
Platform: | Size: 25600 | Author: | Hits:

[VHDL-FPGA-Verilog] dff

Description: 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
Platform: | Size: 1024 | Author: daniel | Hits:

[Crack Hack] DES_Verilog

Description: 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test report, which not only have a simple Notes program [is mainly directed against the waveform simulation], I write is the main control part key generation is partly based on the next version of the original Yasuhiro procedures. The program can also be encrypted can be decrypted, CycloneII optional devices which can run more than 100Mhz.
Platform: | Size: 296960 | Author: jesse | Hits:

[Other] Verilog

Description: verilog的简要教程 基本逻辑门，例如a n d、o r和n a n d等都内置在语言中。 • 用户定义原语（ U D P）创建的灵活性。用户定义的原语既可以是组合逻辑原语，也可以 是时序逻辑原语。 • 开关级基本结构模型，例如p m o s 和n m o s等也被内置在语言中。-Verilog tutorial briefly the basic logic gates, such as and, or and NAND are built in the language. • user-defined primitives (UDP) to create flexibility. User-defined primitives are the combinational logic can be the original language may also be a temporal logic primitives. • The basic structure of switch-level models, such as PMOS and NMOS are also being built in the language.
Platform: | Size: 4169728 | Author: 阿春 | Hits:

[Communication-Mobile] D_BLAST44

Description: MIMO 4*4系统D-BLAST编译码方案，利用ISE仿真环境，verilog编程实现。-MIMO 4* 4 system codec D-BLAST program, using ISE simulation environment, verilog programming implementation.
Platform: | Size: 303104 | Author: 黄虎 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
Platform: | Size: 2041856 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] dff_clk

Description: 简单的D触发器的Verilog描述及，仿真波形-A simple D flip-flop in Verilog description and simulation waveforms
Platform: | Size: 2048 | Author: 李慧静 | Hits:

[VHDL-FPGA-Verilog] 74hc74

Description: 带使能和清零端的D触发器，Verilog实现，有实验说明文档。-With a clear end to enable and D flip-flop, Verilog implementation, there is experimental documentation.
Platform: | Size: 316416 | Author: mypudn0001 | Hits:

[VHDL-FPGA-Verilog] D_latch

Description: actel fpga Verilog D锁存器-actel fpga Verilog D latch
Platform: | Size: 130048 | Author: zhongpeng | Hits:

[VHDL-FPGA-Verilog] Advanced-Digital-Design-with-the-Verilog-HDL-CODE.

Description: 《Verilog HDL高级数字系统设计》（Michael D. Ciletti著） Verilog HDL源代码-" Verilog HDL Advanced Digital System Design" (Michael D. Ciletti a) Verilog HDL source code
Platform: | Size: 1070080 | Author: 曹氏 | Hits:

[Software Engineering] verilog-d-filp-flop

Description: Verilog code of D-Flip Flop
Platform: | Size: 93184 | Author: sandeep | Hits:

[VHDL-FPGA-Verilog] D

Description: FPGA VERILOG实现 D触发器 -FPGA VERILOG D flip-flop
Platform: | Size: 218112 | Author: 李冰 | Hits:
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