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[VHDL-FPGA-Verilog] VERILOG DDS 正弦输出 DL : 0: Verilog 编写
Update : 2011-08-12 Size : 1.75kb Publisher : ymthink
[SCM] DDS+51 DL : 0: 本程序功能: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-this program functions : DDS folder procedures, complete direct digital frequency synthesis, sine, triangle, Three square waveform, and can sweep. can be set up through the keyboard operation frequency waveform parameters and the types of choice and control operations. composed of two parts, "C" folder, for the 51 microcontroller running C Programming Language, "Verilog" folder, use the Verilog language FPGA procedures.
Update : 2025-02-17 Size : 1003kb Publisher : 吴健
[SCM] FPGA--DDS-PhaseMeasure DL : 0: Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.
Update : 2025-02-17 Size : 1.31mb Publisher : haoren
[Program doc] DDS DL : 0: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualcomm
Update : 2025-02-17 Size : 145kb Publisher :
[SCM] Verilog DL : 0: DDS，FPGA产生，用verilog语言实现-DDS, FPGA generated using Verilog language
Update : 2025-02-17 Size : 25kb Publisher :
[Software Engineering] DDS DL : 0: 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Update : 2025-02-17 Size : 545kb Publisher : 毛华站
[Other Embeded program] DDS DL : 0: this a code for DDS in Verilog-this is a code for DDS in Verilog
Update : 2025-02-17 Size : 2kb Publisher : SID17
[VHDL-FPGA-Verilog] DDS DL : 0: Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
Update : 2025-02-17 Size : 82kb Publisher : ray
[SCM] dds DL : 0: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序-ewfreytrgrwf reggwrter rgterthhrgdfs rgdgf egrthg rgreaf rtgerf srfefsf frafgsf frghrsrgwgt
Update : 2025-02-17 Size : 28kb Publisher : nbonwenli
[VHDL-FPGA-Verilog] DDS DL : 0: 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
Update : 2025-02-17 Size : 1.95mb Publisher : 郭帅
[VHDL-FPGA-Verilog] FPGA-DDS DL : 1: 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
Update : 2025-02-17 Size : 2kb Publisher : niuqs
[VHDL-FPGA-Verilog] DDS DL : 0: 同时用verilog 语言编写dds原代码用于生成正余弦波，并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
Update : 2025-02-17 Size : 1kb Publisher : scond
[VHDL-FPGA-Verilog] DDS_VERILOG DL : 0: verilog dds 在发生正弦波时，很好的参考代码-verilog dds
Update : 2025-02-17 Size : 3kb Publisher : 王洋
[VHDL-FPGA-Verilog] dds DL : 0: 在quartus下的DDS设计，Verilog语言，可以产生正弦波、三角波、方波等，频率可调。-Under the DDS in quartus design, Verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
Update : 2025-02-17 Size : 2.51mb Publisher : 米多
[VHDL-FPGA-Verilog] dds DL : 0: verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
Update : 2025-02-17 Size : 2.47mb Publisher : linzi
[VHDL-FPGA-Verilog] dds-design DL : 0: fpga实现dds，实现任意波形输出信，设计代码verilog-dds fpga realization
Update : 2025-02-17 Size : 1kb Publisher : cc
[VHDL-FPGA-Verilog] dds DL : 0: DDS数字式频率合成器利用VERILOG实现，有modelsim仿真图-DDS digital frequency synthesizer using VERILOG realization, modelsim simulation diagram
Update : 2025-02-17 Size : 374kb Publisher :
[SCM] DDS DL : 0: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square wave three, and can sweep. Can be set by keyboard operation frequency parameters and select the waveform type and control operation. Consists of two parts, " C" folder, is used to running on the microcontroller in the 51 C language program, " Verilog" folder, is written in Verilog FPGA program.
Update : 2025-02-17 Size : 423kb Publisher : 王金
[VHDL-FPGA-Verilog] DDS DL : 0: DDS数字频率合成的verilog代码，附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
Update : 2025-02-17 Size : 16mb Publisher : allen-haha
[VHDL-FPGA-Verilog] Verilog-dds DL : 0: 用Verilog实现的DDS，直接频率合成器，相位可调。-Verilog DDS generator
Update : 2025-02-17 Size : 1.13mb Publisher : fu

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