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[VHDL-FPGA-Verilog] verilog fft_64_12

Description: radix-4,利用cordic算法实现复乘单元
Platform: | Size: 13243 | Author: mikehonour@126.com | Hits:

[matlab] fft

Description: fft代码,采用蝶形算法,包括C,matlab和verilog代码-fft code, using butterfly algorithm, including C, matlab and Verilog code
Platform: | Size: 47104 | Author: 陈 | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[VHDL-FPGA-Verilog] cf_fft_256_8

Description: This is a source code of 256 point fft architecture. This code is also available with opencores-This is a source code of 256 point fft architecture. This code is also available with opencores
Platform: | Size: 2048 | Author: Mohan | Hits:

[VHDL-FPGA-Verilog] design

Description: The verilog implementation of 8-point FFT in verilog. Radix 2 Decimation in Frequency.
Platform: | Size: 10240 | Author: Hong-soo | Hits:

[SCM] fft64

Description: 采用verilog代码编写了一个64位的fft，其中蝶形算法采用基2算法-the fft of 64 points
Platform: | Size: 14336 | Author: Evolchs | Hits:

[VHDL-FPGA-Verilog] fft_hdl

Description: 一个 16点 FFT 用基2蝶形运算单元完成，有测试环境。-16 points FFT with a radix-2 butterfly computation unit is completed and test environment.
Platform: | Size: 21504 | Author: wei | Hits:

[VHDL-FPGA-Verilog] fft2

Description: 512点8位基2fft程序。基于 vhdl/verilog。已仿真布线通过。-512 points, eight base 2fft program. Based on vhdl/verilog. Simulation layout has been adopted.
Platform: | Size: 20480 | Author: 包鼎华 | Hits:

[VHDL-FPGA-Verilog] FFT_matlab_hdl_code

Description: FFT 的MATLAB仿真，和Verilog硬件实现-FFT : MATLAB and Verilog simulation
Platform: | Size: 48128 | Author: 李风飞 | Hits:

[Books] counter8andfft

Description: 8位加法器啊，FFT的c++程序 实现加法器的Verilog语言程序-8-bit adder ah, FFT of c++ program to achieve Adder Verilog language program
Platform: | Size: 2048 | Author: 明义 | Hits:

[VHDL-FPGA-Verilog] 256fft

Description:
Platform: | Size: 209920 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] source-(2)

Description: 32k-point FFT verilog
Platform: | Size: 29696 | Author: Jake | Hits:

[VHDL-FPGA-Verilog] FFT

Description: VERILOG CODE FOR FLOATING POINT 8 POINT FFT
Platform: | Size: 16083968 | Author: gsp | Hits:

[source in ebook] multi-verilog

Description: 乘法器。fft。 基2.蝶形运算。旋转因子-Multipliers. fft. Group 2 butterfly. Twiddle factor
Platform: | Size: 1024 | Author: 随身 | Hits:

[Other] 8-fft

Description: FFT 8 PT RDX 2 USING VERILOG
Platform: | Size: 1024 | Author: kiranraj tak | Hits:

[VHDL-FPGA-Verilog] 8-point-pipeline-fft-by-verilog.pdf

Description: 简单的8位基2 流水 fft verilog-Simple 8 base 2 pipelined fft verilog
Platform: | Size: 220160 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] code

Description: c++语言转verilog语言，程序员不需要学习verilog即可对fpga原型进行快速仿真，本例为catapult c语言的fft程序，可以利用catapult转换工具转成verilog语言， 用modelsim进行仿真，并且可以加各种约束。-c++ program translate verilog program。
Platform: | Size: 17408 | Author: wangjun | Hits:

[VHDL-FPGA-Verilog] DIGITAL-SIGNAL-PROCESSING-WITH-FPGA

Description: 数字信号处理的FPGA实现最新版的源代码，涉及FFT变换、IIR、FIR数字滤波器等的verilog及vhdl代码-<digital signal processing with FPGA> (the latest version) . the source code involving FFT transform, IIR, FIR digital filters by verilog and vhdl.
Platform: | Size: 19156992 | Author: Rick007007 | Hits:

[VHDL-FPGA-Verilog] fft_ex1

Description: 基于verilog的FFT设计，使用vivado作为开发平台-Verilog based on the FFT design, the use of vivado as a development platform
Platform: | Size: 4584448 | Author: kan | Hits:

[VHDL-FPGA-Verilog] R2FFT-master

Description: 基2算法fft实现 verilog 快速傅里叶变换(the implemention of fft in radix 2 algorithm)
Platform: | Size: 750592 | Author: slplion | Hits:
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