Search - verilog HDL c

[Other resource] 数据结构c描述习题集答案

Description: 减1计数器一、设计要求用Verilog HDL语言设计一个计数器。要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。二、设计原理输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home / reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input / output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting / 0 : Stop counting); Updown : dollars several self-Canada / reduction Operational control (1 : Since the plus / 0 : Since decrease); load_d
Platform: | Size: 112206 | Author: tutu | Hits:

[Embeded-SCM Develop] 148个verilog hdl小程序（有很多testbench）——

Description: 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
Platform: | Size: 55296 | Author: 地方 | Hits:

[VHDL-FPGA-Verilog] Computer Architecture Handbook on Verilog HDL

Description: Computer Architecture Handbook on Verilog HDL
Platform: | Size: 66560 | Author: 路路 | Hits:

[VHDL-FPGA-Verilog] source3-6

Description: verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，3-6章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 3-6
Platform: | Size: 12288 | Author: 余月森 | Hits:

[VHDL-FPGA-Verilog] source7-8

Description: verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，7-8章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 7- 8
Platform: | Size: 8192 | Author: 余月森 | Hits:

[VHDL-FPGA-Verilog] source9-10

Description: verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10
Platform: | Size: 15360 | Author: 余月森 | Hits:

[VHDL-FPGA-Verilog] source11-12

Description: verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，11-12章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code 11-10-12 Cap
Platform: | Size: 9216 | Author: 余月森 | Hits:

[VHDL-FPGA-Verilog] 数据结构c描述习题集答案

Description: 减1计数器一、设计要求用Verilog HDL语言设计一个计数器。要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。二、设计原理输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d
Platform: | Size: 111616 | Author: tutu | Hits:

[Books] Verilog_HDL_Hardware_Description_Language

Description: 正式出版物《Verilog HDL 硬件描述语言》一书的精美 PDF 电子版。-official publications "Verilog HDL Hardware Description Language," a book of exquisite electronic PDF version.
Platform: | Size: 4767744 | Author: bigheadmonk | Hits:

[Other] pli_handbook_examples_pc

Description: pli_handbook_examples_pc verilog hdl 与C的接口的典型例子-pli_handbook_examples_pc verilog and C hdl The classic example of the interface
Platform: | Size: 372736 | Author: maliang | Hits:

[VHDL-FPGA-Verilog] VerilogHDLPLI

Description: Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
Platform: | Size: 1024 | Author: 杨锐 | Hits:

[Other] ImplementationFromAlgorithmDesigntoHardwareLogic.r

Description: 第一章数字信号处理、计算、程序、算法和硬线逻辑的基本概念第二章 Verilog HDL设计方法概述第三章 Verilog HDL的基本语法第四章不同抽象级别的Verilog HDL模型第五章基本运算逻辑和它们的Verilog HDL模型第六章运算和数据流动控制逻辑-the first chapter of digital signal processing and computing procedures, hard-line algorithm and the basic logic of the concept of the second chapter of Verilog HDL design methods outlined in the third chapter Verilo g HDL basic grammar Chapter 4 different levels of abstract Verilog HDL model V basic arithmetic logic and their Verilog HDL model of the sixth chapter operations and data flow control logic
Platform: | Size: 421888 | Author: 陈亨利 | Hits:

[MiddleWare] pwm_VerilogHDLV1.1

Description: 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX　ＰＬＵＳ　ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
Platform: | Size: 232448 | Author: wjz | Hits:

[Software Engineering] FromAlgorithmToAchievmentOfHardware

Description: 从算法设计到硬线逻辑的实现 Verilog HDL牛人编写的有关经典书籍，其中包含很多例子-From algorithm design to hard-line Verilog HDL logic realize cattle were prepared by the classic book, which contains many examples
Platform: | Size: 830464 | Author: 杨轶帆 | Hits:

[VHDL-FPGA-Verilog] ac97_verilog_sourcecode

Description: AC97芯片的verilog实现，有兴趣可以研究下。verilog是一种硬件开发语言，语法与c类似。与VHDL并列为IC开发两大编程语言-AC97 chip Verilog realize, who are interested can study. Verilog is a hardware development language, grammar and c similar. IC with VHDL as a programming language to develop two
Platform: | Size: 124928 | Author: 小步 | Hits:

[VHDL-FPGA-Verilog] 16bitCLA

Description: 基于Verilog HDL的16位超前进位加法器分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
Platform: | Size: 7168 | Author: 韩伟 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的数字系统建模。被建模的数字系统对象的复杂性可以介于简单的门和完整的电子数字系统之间。数字系统能够按层次描述，并可在相同描述中显式地进行时序建模。　　Verilog HDL 语言具有下述描述能力：设计的行为特性、设计的数据流特性、设计的结构组成以及包含响应监控和设计验证方面的时延和波形产生机制。所有这些都使用同一种建模语言。此外，Verilog HDL语言提供了编程语言接口，通过该接口可以在模拟、验证期间从设计外部访问设计，包括模拟的具体控制和运行。 -Verilog HDL语言不仅定义了语法，而且对每个语法结构都定义了清晰的模拟、仿真语义。因此，用这种语言编写的模型能够使用Verilog仿真器进行验证。语言从C编程语言中继承了多种操作符和结构。Verilog HDL提供了扩展的建模能力，其中许多扩展最初很难理解。但是，Verilog HDL语言的核心子集非常易于学习和使用，这对大多数建模应用来说已经足够。当然,完整的硬件描述语
Platform: | Size: 32106496 | Author: 杨恩源 | Hits:

[Other] Verilog-HDL

Description: Verilog-HDL实践与应用系统设计，Verilog-HDL语言是类似于C语言的一种硬件开发语言。-Practice and Application of Verilog-HDL design, Verilog-HDL language is similar to the C language, a hardware development language.
Platform: | Size: 15431680 | Author: 陈俊直 | Hits:

[VHDL-FPGA-Verilog] A-Verilog-HDL-Test-Bench-Primer

Description: 经典Verilog HDL教程，很不错，我就是用它来学习Verilog，听说过C++ primer吧。肯定是很有价值的。-Classic Verilog HDL tutorial
Platform: | Size: 58368 | Author: 占欣 | Hits:

[Program doc] Verilog-HDL

Description: verilog HDL程序入门，很好学，基本和C语言一样，几天就可以简单的编程-verilog HDL program entry, very good school, Basic and C language, a few days can be a simple programming
Platform: | Size: 11424768 | Author: 李文帅 | Hits:

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