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Description: 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
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Size: 28424 |
Author: 于飞 |
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Description: VHDL黄金版,本人费了九牛才找到,帮助初学者入门-VHDL version, I spent nine cattle to find help beginners entry
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Size: 203582 |
Author: 江涛 |
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Description: 51的VERILOG代码!适用于Xilinx的FPGA-51 VERILOG code! In Xilinx FPGA
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Size: 1220608 |
Author: 林建加 |
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Description: VHDL黄金版,本人费了九牛才找到,帮助初学者入门-VHDL version, I spent nine cattle to find help beginners entry
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Size: 203776 |
Author: 江涛 |
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Description: 这时manchesite编码,VERILOG语言,VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting
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Size: 9216 |
Author: 李无志 |
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Description: 此文件为B3ZS编解码,本人在我公司的通信设备上已经通过了试验,编写语言为verilog,解压无密码。-B3ZS coding and decoding, I in my company's communications equipment has passed the test, prepare for the Verilog language, without extracting passwords.
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Size: 1024 |
Author: 陆贵山 |
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Description: 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
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Size: 27648 |
Author: 于飞 |
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Description: 用Verilog HDL实现I2C总线功能,对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.
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Size: 889856 |
Author: 司法 |
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Description: iic 总线 verilog 源代码
标准i2c总线, 有sda scl 时钟,频率自定-IIC bus standard Verilog source code i2c bus, has sda scl clock, the frequency of self-
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Size: 2048 |
Author: johnnyz |
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Description: Verilog教程,不知道没有人传过-Verilog tutorial, I do not know and no one had Biography
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Size: 4204544 |
Author: 小罗 |
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Description: 这是一有很好价值的verilog教程,本人就因此获意非浅,再次贡献给大家,希望大家有所帮助.-This is a very good value Verilog tutorial, I am going to be intended to greatly therefore, contribute to the U.S. again, I hope everybody help.
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Size: 143360 |
Author: ixia |
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Description: verilog 我自己写得按单脉冲发生器,通过了综合和仿真,和频率可变的正弦波发生器,-verilog I write by a single pulse generator, through the synthesis and simulation, and variable frequency sine wave generator,
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Size: 1024 |
Author: 潘见 |
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Description: Verilog实现的I2C协议,直接在ISE下打开就可以-Verilog implementation I2C protocol to open directly in the ISE can be
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Size: 212992 |
Author: Roy |
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Description: 《无线通信的FPGA设计》里的源码,verilog语言,开发环境我选的VHDL(没有Verilog,代替一下,两个相通)-" Wireless Communications FPGA design" where the source code, verilog language, development environment, I chose VHDL (no Verilog, instead of what, two interlinked)
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Size: 142336 |
Author: 赵晴 |
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Description: fpga使用代码大全,很有用的,,谢谢下载,我没什么说的了,住学习愉快-fpga using the Code Complete, very useful, Thank you to download, I have nothing to say about it, learning to live happily
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Size: 244736 |
Author: 苟春国 |
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Description: 这资料主要是介绍一些verilog的一些实用程序,希望对大家有用。-This information is to introduce some practical procedures of some Verilog, I hope useful for everyone.
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Size: 117760 |
Author: 何标 |
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Description: cpu仿真,提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words
in this short file
how can I do?
just tell you the simulated file and vivado system is 2015)
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Size: 200704 |
Author: momotou
|
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Description: verilog语言资料,很有效的,比夏雨闻的要好用易懂,希望有帮助(Verilog language data, very effective, better than Xia Yu's smell, easy to understand, and I hope it helps.)
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Size: 470016 |
Author: 冯猜猜2 |
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Description: 基础的几个verilog代码实现,讲到case和task的使用。(basic verilog,use case and task ,very usual, i want some help to achieve the design of delta and sigma fractional_n divider.)
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Size: 88064 |
Author: sana00 |
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Description: 平台上已有本书代码,缺少对应的电子版的书,特此分享。(There are already book codes on the platform, and there is no corresponding electronic version of the book, so I would like to share with you.)
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Size: 39305216 |
Author: Brill |
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