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[Embeded-SCM Develop] verilog实例 [43项] DL : 0: 嵌入式可编程器件CPLD的典型实例压缩包，共计43个源码文件。使用ALTERA的 Muxplus 软件即可编辑仿真相关软件可在教育网ftp下载[天网查询，有很多站点提供]-Embedded Programmable CPLD in a typical example of compressed, for a total of 43 source document. Altera Muxplus use the software can edit simulation software available from the Education Network ftp download [days Web inquiries, many sites provide]
Update : 2025-02-17 Size : 177kb Publisher : 吴旭辉
[Books] Verilog-Semantics DL : 0: Synthesizable Verilo---syntax and semantics一本很好的关于verilog可综合设计的参考书-Synthesizable Verilo--- syntax and semantics a good Verilog synthesis of the reference design
Update : 2025-02-17 Size : 292kb Publisher : 肖磊
[Books] verilog reference guide DL : 0: 一本全面的verilog参考书-a comprehensive reference book Verilog
Update : 2025-02-17 Size : 199kb Publisher : 肖磊
[Other Embeded program] 发一个基于ModelSim仿真的Verilog源代码包 DL : 0: 发一个基于ModelSim仿真的Verilog源代码包-made a ModelSim simulation based on the Verilog source code
Update : 2025-02-17 Size : 73kb Publisher : 阿乐
[Other Embeded program] Verilog 语法速查手册 DL : 0: Verilog 语法速查手册，做成了一个页面形式，方便Verilog开发人员查询！-Verilog Grammar Check manual, it would be a one page form to facilitate the development of Verilog staff inquiries!
Update : 2025-02-17 Size : 24kb Publisher : 飞扬
[VHDL-FPGA-Verilog] verilog实现ALU的源代码 DL : 0: verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!
Update : 2025-02-17 Size : 1kb Publisher : 飞扬
[VHDL-FPGA-Verilog] Verilog&Vhdl混语言对SDRAM的控制源代码 DL : 0: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Update : 2025-02-17 Size : 244kb Publisher : 飞扬
[VHDL-FPGA-Verilog] Verilog HDL设计练习进阶 DL : 0: 初学verilog HDL时找的好资料大家共享-Beginners should try to find a good share information
Update : 2025-02-17 Size : 665kb Publisher : chencsw
[VHDL-FPGA-Verilog] hjs Verilog DL : 0: 是verilog例子。初级适用。包括了简单的例子。-example. The initial application. Including a simple example.
Update : 2025-02-17 Size : 39kb Publisher : 黄先生
[VHDL-FPGA-Verilog] Verilog DHL数字钟 DL : 0: 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
Update : 2025-02-17 Size : 2kb Publisher : 谢树扬
[Books] A Verilog HDL Test Bench Primer DL : 0: Lattice公司的A Verilog HDL Test Bench Primer应用手册-Lattice A Verilog HDL Test Bench Primer Handbook
Update : 2025-02-17 Size : 56kb Publisher : 陈正一
[Communication] verilog for uart DL : 0: 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver/transmitter (UART) can be programmed to control computer attached to the serial device interface microchips. Details, provide it to the computer RS-High ... UART also provide a certain number of data buffer, computer equipment and serial data stream can maintain the same speed.
Update : 2025-02-17 Size : 9kb Publisher : 李志
[VHDL-FPGA-Verilog] verilog-a DL : 0: verilogA的教材，详细的介绍了语言的用法，主要是用于模拟电路系统建模和仿真。-verilogA materials, detail the usage of the language was mainly used to simulate the circuit system modeling and simulation.
Update : 2025-02-17 Size : 997kb Publisher : 赵晓迪
[Books] verilog DL : 1: verilog（一大牛写的）个人感觉很适合初学者使用，讲解比较详细-verilog [a cow' s Writing] personal feeling is very suitable for beginners to use, explain in more detail
Update : 2025-02-17 Size : 485kb Publisher : yu binbin
[Other] Digital_Vlsi_Design_With_Verilog_A_Textbook_From_ DL : 0: Digital Vlsi Design With Verilog A Textbook From Silicon Valley Technical Institute.pdf Thisbookisbasedonthelabexercisesandorderofpresentationofacourse developedandgivenbytheauthoroveraperiodofyearsatSiliconValleyTech- nicalInstitute,SanJose,California. Atthetime,totheauthor°Psbestknowledge,thiscoursewastheonlyoneeve givenwhich(a)presentedtheentireveriloglanguage (b)involvedimplementation ofafull-duplexserdessimulationmodel or(c)includeddesignofasynthesizable digitalPLL.
Update : 2025-02-17 Size : 3.3mb Publisher : Frank
[Other] verilog-A_library DL : 0: Complete Verilog-A library for analog blocks, like ADC, DAC, amplifiers
Update : 2025-02-17 Size : 79kb Publisher : zhanglh
[VHDL-FPGA-Verilog] verilog-a-lrm-1-0 DL : 0: Verilog-A Language Reference Manual Analog Extensions to Verilog HDL
Update : 2025-02-17 Size : 211kb Publisher : bassa
[Other] verilog-a DL : 0: 一本关于Verilog-a的设计语言基础，对初学者很重要。-A book on Verilog-a design language based on the beginner is very important.
Update : 2025-02-17 Size : 211kb Publisher : neil
[Other] cadence-verilog-a-language-reference DL : 0: 这个是cadence公司的verilog-a学习手册，非常全面，是模拟集成电路设计的好助手-This is the company' s cadence verilog-a study manual, very comprehensive, is the analog integrated circuit design, a good assistant
Update : 2025-02-17 Size : 978kb Publisher : Mr Chen
[Software Engineering] verilog-a-lrm-1-0 DL : 0: The information contained in this draft manual represents the definition of the Verilog-A hardware description language as proposed by OVI (Analog TSC) as of January, 1996. Open Verilog International makes no warranties whatsoever with respect to the completeness, accuracy, or applicability of the information in this draft manual to a user’s requirements. This language is not yet fully defined and is subject to change. It is suitable for learning how to do analog modeling and as a vehicle for providing feedback to the standards committee. Verilog- A should not be used for production design and development.
Update : 2025-02-17 Size : 211kb Publisher : bkaraca

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